Abstract A semiconductor bucket brigade shift register having a plurality of cells, each cell embodying a transistor and a large capacitance element coupled across the base and the collector contacts of the transistor. Each cell, includes a first layer of insulating material bonded to the surface of the semiconductor body, a second layer of polycrystalline silicon overlying the first layer, a third layer of insulating material over the second layer, emitter, base, and collector contacts to the body of semiconductor material extending through the first, second, and third layers and insulated from the second layer, an electrical connection between the base contact and the second layer of polycrystalline material, and a relatively large surface area of a conductive layer in contact with the collector contact overlying at least in part the second layer.
The semiconductor cell structure of claim 1 wherein said third layer of insulating material is a layer of thermal silicon oxide.
Claim 2
Dependent Claim
25 words
The semiconductor structure of claim 2 wherein said layer of thermal silicon oxide has a thickness in the range of 1,000 to 2, 000 angstroms.
Claim 3
Dependent Claim
29 words
The semiconductor cell structure of claim 1 wherein the capacitance between the base and collector contacts of the transistor is in the range of one-half to 2 pico farads.
Claim 4
Dependent Claim
19 words
The semiconductor cell structure of claim 1 wherein the transistor is insulated from adjacent cells by a PN junction.
Claim 5
Dependent Claim
22 words
The semiconductor cell structure of claim 1 wherein the transistor is at least insulated in part from adjacent cells by dielectric material.
Claim 6
Dependent Claim
244 words
In a planar integrated circuit shift register semiconductor structure on a monocrystalline semiconductor body, where each cell of the shift register embodies a field effect transistor and a capacitance element coupled across the gate electrode and the drain region of the field effect transistor, the improvement comprising: spaced diffused regions in said body, each of said regions serving as a drain region for a first field effect transistor and a source region for an adjacent second field effect transistor, a first layer of insulating material on the surface of the semiconductor body, a second layer of doped polycrystalline silicon overlying said first layer and separated into a plurality of individual areas, each of said areas overlying the gate region of the associated field effect transistor and at least a portion of an associated diffused region, a third layer of thermal silicon oxide insulating material over said second layer, a fourth layer of a conductive material overlying said third layer separated into a plurality of individual areas, each of said areas overlying at least in part an associated individual area of said second layer and in ohmic contact with the respective drain region of the transistor, each of said areas of said second layer operating as a first conductor of a capacitor, the areas of said fourth layer and said drain region of said semiconductor body operating as the second conductor of a capacitor, and the first and third insulating layers serving as a dielectric.