Patent US3768455A successfully refreshed from Google Patents.
Patent US3909541A successfully refreshed from Google Patents.
US3909541A
Expired / Lapsed
US
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Low-speed framing arrangement for a high-speed digital bitstream
Assignee: AT&T Inc
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Filing: 1974-03-11
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Granted: 1975-09-30
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Expires: 1994-03-11
Abstract
Abstract A high-speed digital bitstream comprising information, from a plurality of multiplexed channels, and framing bits is unconditionally divided into a number of lower speed bitstreams. The lower speed bitstreams are then conditionally divided to form a new group of bitstreams, and the new bitstreams are examined by a framing detector. The framing detector shifts the timing of the conditional division in relation to the lower speed bitstreams until a predetermined framing pattern appears among the new bitstreams. The nature of the occurrence of the framing pattern identifies the operating mode of the unconditional division. The new bitstreams are switched, in accordance with the operating mode, to provide a plurality of outputs wherein each output corresponds to a particular multiplexed channel regardless of the operating mode of the unconditional division.
Inventors
- 👤 Richard Thomas Bobilin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 17:54
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/02; H04L25/14; H04J; H04J3/00; H04J3/02; H04J3/04; H04J3/06; H04J3/0602; H04J3/0605
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
238 words
In a time division multiplexed digital transmission system wherein the transmitted bitstream comprises a plurality of channels in a framed format, receiving apparatus for demultiplexing the bitstream comprising: means for nonsynchronously distributing the bits of the received bitstream successively to form N low-speed digital bitstreams, each of the N digital bitstreams comprising bits corresponding to invariable positions in the received bitstream; dividing means responsive to the received bitstream for producing P phased output signals; switching means connected to receive the P phased output signals and the N low-speed bitstreams serving to redistribute the bits of the N bitstreams to supply a digital signal to each of M outputs; and detecting means for identifying any one of N possible frAming patterns among the N low-speed bitstreams, said detecting means supplying a signal to said dividing means to shift the P phased outputs thereof in relation to the bits of said N digital bitstreams until the occurrence of one of N framing patterns, said detecting means identifying the framing pattern that does occur which indicates the operating mode of said means for nonsynchronously distributing and in response serving to signal the same to said switching means which in accordance with the operating mode redistributes the bits of the N digital bitstreams to provide a digital signal for each of said M outputs corresponding to one of said plurality of channels wherein N, P and M are integers greater than one.
Claim 2
Dependent Claim
238 words
In a time division multiplexed digital transmission system wherein the transmitted bitstream comprises a plurality of channels in a framed format, receiving apparatus for demultiplexing the bitstream comprising: means for nonsynchronously distributing the bits of the received bitstream successively to form N low-speed digital bitstreams, each of the N digital bitstreams comprising bits corresponding to invariable positions in the received bitstream; dividing means responsive to the received bitstream for producing P phased output signals; switching means connected to receive the P phased output signals and the N low-speed bitstreams serving to redistribute the bits of the N bitstreams to supply a digital signal to each of M outputs; and detecting means for identifying any one of N possible frAming patterns among the N low-speed bitstreams, said detecting means supplying a signal to said dividing means to shift the P phased outputs thereof in relation to the bits of said N digital bitstreams until the occurrence of one of N framing patterns, said detecting means identifying the framing pattern that does occur which indicates the operating mode of said means for nonsynchronously distributing and in response serving to signal the same to said switching means which in accordance with the operating mode redistributes the bits of the N digital bitstreams to provide a digital signal for each of said M outputs corresponding to one of said plurality of channels wherein N, P and M are integers greater than one.
Claim 3
Dependent Claim
25 words
The demultiplexing apparatus as defined in claim 1 wherein the number of N digital bitstreams is 2 and the number of M outputs is 2.
Claim 4
Dependent Claim
37 words
The demultiplexing apparatus as defined in claim 2 wherein said dividing means produces two coexisting output signals displaced in phase from each other and said detecting means is capable of identifying either of two possible framing patterns.
Claim 5
Dependent Claim
201 words
Demultiplexing apparatus for demultiplexing a time division multiplexed high-speed bitstream comprising successive frames separated by stuffing and parity bits that convey framing information and wherein each frame corresponds to a plurality of multiplexed low-speed bitstreams, said demultiplexing apparatus comprising: sampling means for unconditionally dividing the high-speed bitstream into a plurality of medium-speed bitstreams wherein the duration of each time slot in the medium-speed bitstreams is equal to the factor of the division times the duration of a time slot in the high-speed bitstream; dividing means for separating each of said medium-speed bitstreams into a plurality of low-speed bitstreams; detecting means for monitoring selected low-speed bitstreams, said detecting means supplying a feedback signal to said dividing means to alter the output of the same until said detecting means identifies the occurrence of a framing pattern produced by the stuffing and parity bits, the nature of the occurrence of said pattern also serving to indicate the operating mode of said sampling means; and switching means connected to receive said low-speed bitstreams and having a plurality of outputs, said switching means being operative in response to a mode signal from said detecting means to selectively couple said low-speed bitstreams to said plurality of outputs.
Claim 6
Dependent Claim
201 words
Demultiplexing apparatus for demultiplexing a time division multiplexed high-speed bitstream comprising successive frames separated by stuffing and parity bits that convey framing information and wherein each frame corresponds to a plurality of multiplexed low-speed bitstreams, said demultiplexing apparatus comprising: sampling means for unconditionally dividing the high-speed bitstream into a plurality of medium-speed bitstreams wherein the duration of each time slot in the medium-speed bitstreams is equal to the factor of the division times the duration of a time slot in the high-speed bitstream; dividing means for separating each of said medium-speed bitstreams into a plurality of low-speed bitstreams; detecting means for monitoring selected low-speed bitstreams, said detecting means supplying a feedback signal to said dividing means to alter the output of the same until said detecting means identifies the occurrence of a framing pattern produced by the stuffing and parity bits, the nature of the occurrence of said pattern also serving to indicate the operating mode of said sampling means; and switching means connected to receive said low-speed bitstreams and having a plurality of outputs, said switching means being operative in response to a mode signal from said detecting means to selectively couple said low-speed bitstreams to said plurality of outputs.
Claim 7
Dependent Claim
171 words
The demultiplexing apparatus according to claim 4 wherein said sampling means comprises first and second bistable means, clocking means and delaying means, said first and second bistable means each having one input connected to receive the high-speed bitstream and a toggle unit, said clocking means in circuit relationship with the high-speed bitstream and providing an output signal having a frequency corresponding to half the bit rate of the high-speed bitstream, and the output of said clocking means being directly applied to the toggle input of said first bistable means and applied to the toggle input of said second bistable means through said delaying means such that when the output signal of said clocking means toggles said first bistable means to sample a bit of the high-speed bitstream to produce an output for a first medium-speed bitstream said second bistable means is subsequently toggled by the same output signal of said clocking means to sample the next successive bit of the high-speed bitstream to provide an output for a second medium-speed bitstream.
Claim 8
Dependent Claim
144 words
The demultiplexing apparatus according to claim 5 wherein said dividing means comprises a plurality of bistable means each having a toggle input and half of which have an input connected to receive the first medium-speed bitstream and the other half of which have an input connected to receive the second medium-speed bitstream, and multiphasing means connected to receive the output of said clocking Means for producing a plurality of output signals staggered in phase, each output signal of said multiphasing means being applied to the toggle inputs of a pair of bistable means, the first of said pair connected to receive the first medium-speed bitstream and the second of said pair connected to receive the second medium-speed bitstream, and said plurality of bistable means sampling the medium-speed bitstreams in response to the output of said multiphasing means to provide the plurality of low-speed bitstreams.
Claim 9
Dependent Claim
77 words
The demultiplexing apparatus according to claim 6 wherein said detecting means comprises first and second gating means each connected to receive a pair of low-speed bitstreams from said dividing means such that said first gating means produces an output signal indicative of framing synchronization when said sampling means is operating in a first mode while said second gating means produces an output signal indicative of framing synchronization when said sampling means is operating in a second mode.
Claim 10
Dependent Claim
100 words
The demultiplexing apparatus according to claim 6 further comprising logical means connected to receive one of the low-speed bitstreams applied to said first gating means and a low-speed bitstream from said dividing means, said logical means acting in response to one of the output signals from said multiphasing means and the mode indication from said detecting means to provide a first output signal to said switching means indicative of information bits and another output signal to said second gating means for producing an output signal indicative of framing synchronization when said first sampling means is operating in the second mode.
Claim 11
Dependent Claim
22 words
The demultiplexing apparatus according to claim 8 wherein said switching means has a configuration corresponding to a six pole, double throw switch.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-09-29 | 1979-03-31 | 1979-09-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-09-29 | 1983-03-31 | 1983-09-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-09-29 | 1987-03-31 | 1987-09-30 | $7700.00 | Window Closed / Lapsed |