US3602647A
Expired / Lapsed
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Control signal transmission in time division multiplex system communications
Assignee: Fujitsu Ltd
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Filing: 1968-10-16
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Granted: 1971-08-31
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Expires: 1988-10-16
Abstract
Abstract In a control signal transmission system of a time division multiplex system a plurality of series pulse code modulation trains including binary data bits and ringing bits or signalling bits are provided in parallel. A single series pulse code modulation train is derived and is comprised exclusively of ringing bits. In the single series pulse code modulation train, the minimum number of ringing bits required for transmitting ringing information in a unit time is maintained. The remaining bits of the single series pulse code modulation train are replaced with synchronizing signals.
Inventors
- 👤 Masao Kawashima
- 👤 Shigehiko Hinoshita
- 👤 Tsukumo Higeta
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 15:27
CPC Classifications
H; H03; H03K; H03K7/00; H04; H04J; H04J3/00; H04J3/02; H04J3/06; H04J3/0602; H04Q; H04Q11/00; H04Q11/04
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
206 words
In a time division multiplex system, a control signal transmission system comprising: a plurality of incoming serial multiplexed pulse code modulation pulse trains including at least one signalling bit per channel; series to parallel conversion means associated with each pulse train for changing the series bit relationship to a parallel one and for distributing the parallel bits to individual transmission paths of an output group of transmission paths; parallel bit assembly means connected to a plurality of output groups and having output means with the same number of parallel transmission paths as each output group for interleaving the parallel bits from each output group onto corresponding transmission paths in said output means whereby one of the transmission paths of said output means transmits only signalling bits; circuit means connected to said parallel bit assembly means for deriving a single series pulse code modulation train exclusively of signalling bits and maintaining in said single series pulse code modulation train the minumum number of signalling bits required for transmitting signalling information in a unit time; and output means connected to said circuit means for replacing the remaining bits of said single series pulse code modulation train with control signals and transmitting the pulse code modulation trains in parallel.
Claim 2
Dependent Claim
206 words
In a time division multiplex system, a control signal transmission system comprising: a plurality of incoming serial multiplexed pulse code modulation pulse trains including at least one signalling bit per channel; series to parallel conversion means associated with each pulse train for changing the series bit relationship to a parallel one and for distributing the parallel bits to individual transmission paths of an output group of transmission paths; parallel bit assembly means connected to a plurality of output groups and having output means with the same number of parallel transmission paths as each output group for interleaving the parallel bits from each output group onto corresponding transmission paths in said output means whereby one of the transmission paths of said output means transmits only signalling bits; circuit means connected to said parallel bit assembly means for deriving a single series pulse code modulation train exclusively of signalling bits and maintaining in said single series pulse code modulation train the minumum number of signalling bits required for transmitting signalling information in a unit time; and output means connected to said circuit means for replacing the remaining bits of said single series pulse code modulation train with control signals and transmitting the pulse code modulation trains in parallel.
Claim 3
Dependent Claim
18 words
In a time division multiplex system as claimed in claim 1, wherein said control signals are synchronizing signals.
Claim 4
Dependent Claim
50 words
In a time division multiplex system as claimed in claim 1, wherein said code means provides said series pulse code modulation trains in two groups of parallel pulse code modulation trains to provide twice the multiplexity provided by a single pulse code modulation train in the same transmission frequency band.
Claim 5
Dependent Claim
42 words
In a time division multiplex system as claimed in claim 3, wherein each of said bits is in a bit time slot and each parallel pulse code modulation train comprises a single pulse code modulation train provided in full bit time slots.
Claim 6
Dependent Claim
40 words
In a time division multiplex system as claimed in claim 3, wherein each of said bits is in a bit time slot and said two groups of parallel pulse code modulation trains are provided in the same bit time slots.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-08-30 | 1975-03-01 | 1975-08-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-08-30 | 1979-03-01 | 1979-08-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-08-30 | 1983-03-01 | 1983-08-31 | $7700.00 | Window Closed / Lapsed |