US3639693A
Expired / Lapsed
US
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Time division multiplex data switch
Assignee: Telent Technologies Services Ltd
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Filing: 1968-11-22
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Granted: 1972-02-01
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Expires: 1988-11-22
Abstract
Abstract A time division multiplex data switch wherein any one of a plurality of input channels forming a plurality of input groups may be switched to any one of a plurality of output channels forming a plurality of output groups, which includes individually synchronized bit distributors associated with each input group, for distributing the bits to a plurality of single-bit stores, each associated with a channel, and a single-time division highway controlled by a dynamic memory.
Inventors
- 👤 William F Bartlett
- 👤 William A Oswald
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 11:28
CPC Classifications
H; H04; H04Q; H04Q11/00; H04Q11/04; H04Q11/08
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
267 words
A time division multiplex data switch for switching any one input channel included in one of a plurality of groups of multiplexed input channels to any one of a plurality of groups of multiplexed output channels comprising input bit distributor means for demultiplexing said groups of input channels and first single-bit storage means including a plurality of single-bit stores for individually storing the bits of the input channels of respective groups in different stores for a time equal to the repetition rate of said multiplexed input channels, cross-office switching means connected to said single-bit storage means for selectively gating the bits individually stored therein to respective groups of output channels in timed sequence to produce said groups of multiplexed output channels, including a single-multiplex highway and matrix means connected to the outputs of said single-bit stores for sequentially connecting said stores to said highway in a selectively controlled order, processor means responsive to a switching instruction for controlling the sequence of the stored bits switched by said cross-office switching means to said multiplex highway so as to connect a given input channel to a given output channel, including a dynamic memory providing a time slot for each output channel connected in control of said matrix means and control means for storing said switching instruction in said memory, and second single-bit storage means including one single-bit store for each group of output channels and gating means for connecting said multiplex highway to the single-bit stores of said second single-bit storage means in the order in which the time slots of said memory are assigned to said output channels.
Claim 2
Dependent Claim
267 words
A time division multiplex data switch for switching any one input channel included in one of a plurality of groups of multiplexed input channels to any one of a plurality of groups of multiplexed output channels comprising input bit distributor means for demultiplexing said groups of input channels and first single-bit storage means including a plurality of single-bit stores for individually storing the bits of the input channels of respective groups in different stores for a time equal to the repetition rate of said multiplexed input channels, cross-office switching means connected to said single-bit storage means for selectively gating the bits individually stored therein to respective groups of output channels in timed sequence to produce said groups of multiplexed output channels, including a single-multiplex highway and matrix means connected to the outputs of said single-bit stores for sequentially connecting said stores to said highway in a selectively controlled order, processor means responsive to a switching instruction for controlling the sequence of the stored bits switched by said cross-office switching means to said multiplex highway so as to connect a given input channel to a given output channel, including a dynamic memory providing a time slot for each output channel connected in control of said matrix means and control means for storing said switching instruction in said memory, and second single-bit storage means including one single-bit store for each group of output channels and gating means for connecting said multiplex highway to the single-bit stores of said second single-bit storage means in the order in which the time slots of said memory are assigned to said output channels.
Claim 3
Dependent Claim
48 words
A time division multiplex date switch as defined in claim 1 wherein the number of input channels in at least one group of input channels and the number of output channels in at least one group of output channels differs from the number in the other respective groups.
Claim 4
Dependent Claim
44 words
A time division multiplex data switch as defined in claim 1 wherein the time slot assignment of output channels in said memory provides for an interlacing of data to said multiplex highway in accordance with the number of output channels assigned to each group.
Claim 5
Dependent Claim
69 words
A time division multiplex data switch as defined in claim 1 wherein each input channel is divided into a plurality of input submultiplex channels and each output channel is divided into a plurality of output submultiplex channels, a first single-bit store being provided for each input submultiplex channel and each time slot in said memory being formed of a plurality of subslots each assigned to an output submultiplex channel.
Claim 6
Dependent Claim
54 words
A time division multiplex data switch as defined in claim 4 wherein said instruction means includes first register means for storing a unique signal representative of a first single-bit store and timing means for gating said unique signal into said memory at the proper time to store said signal in a certain subslot thereof.
Claim 7
Dependent Claim
107 words
A time division multiplex data switch as defined in claim 5 wherein said timing means includes a first counter, means for storing in said first counter the number of the subslot in said memory to which a unique signal is to be transferred, a source of clock pulses, trigger means for applying said clock pulses to said first counter to drive said counter to zero in synchronism with the start of the cycle of said memory, said first counter providing a transfer signal upon reaching the count of zero, and a first gate connecting said first register means to said memory upon receipt of said transfer signal.
Claim 8
Dependent Claim
41 words
A time division multiplex data switch as defined in claim 6 wherein said timing means further includes additional means for successively gating said unique signal from said first register means into said memory in the corresponding subslot of consecutive submultiplex channels.
Claim 9
Dependent Claim
73 words
A time division multiplex data switch as defined in claim 7 wherein said additional means includes a second counter producing a transfer signal upon reaching a count equal to the number of time slots allocated to a submultiplex channel, and second trigger means for selectively applying clock pulses from said source to said second counter, said transfer pulse being applied to said first gate to connect said first register means to said memory.
Claim 10
Dependent Claim
45 words
A time division multiplex data switch as defined in claim 8 wherein said timing means further includes a second gate connected to said first gate for applying either the transfer signal from said first counter or from said second counter to actuate said first gate.
Claim 11
Dependent Claim
56 words
A timE division multiplex data switch as defined in claim 8 wherein said additional means further includes a frame counter connected to said second counter for counting said transfer signals and providing a reset signal upon reaching a count equal to the number of submultiplex channels, said reset signal serving to reset said second trigger means.
Claim 12
Dependent Claim
49 words
A time division multiplex data switch as defined in claim 10 wherein said timing means further includes a toggle circuit for selectively disabling said trigger means or blocking the transfer signal from said first counter to effect control over data relating to a submultiplex channel or a channel, respectively.
Claim 13
Dependent Claim
30 words
A time division multiplex data switch as defined in claim 1 wherein synchronous detector means are connected from each input group to each bit distributor for ensuring synchronous operation thereof.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-01-31 | 1975-08-02 | 1976-02-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-01-31 | 1979-08-02 | 1980-02-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-01-31 | 1983-08-02 | 1984-02-01 | $7700.00 | Window Closed / Lapsed |