MIS type semiconductor device having high operating voltage and manufacturing method

Claim 1

A METHOD OF MANUFACTURING AN INSULATED GATE TYPE FIELD EFFECT TRANSISTOR, COMPRISING THE STEP OF: A. FORMING A FIRST INSULATING FILM ON A SEMICONDUCOR SUBSTRATE, B. FORMING IN SAID FIRST INSULATING FILM, A FIRST HOLE EXTENDING TO THE SURFACE OF THE SUBSTRATE, C. INTRODUCING A CONDUCTIVE TYPE IMPURITY DETERMINING WHICH IS DIFFERENT FROM THAT OF THE SUBSTRATE, THROUGH SAID FIRST HOLE INTO SAID SUBSTRATE TO FORM A FIRST REGION OF A RELATIVELY LOW IMPURITY CONCENTRATION, D. FORMING A SECOND INSULATING FILM IN SAID HOLE E. FORMING IN SAID FIRST AND SECOND INSULATING FILMS, A SECOND HOLE EXPOSING A SURFACE PORTION OF SAID FIRST REGION, AND A THIRD HOLE EXPOSING A SURFACE PORTION OF SAID SUBSTRATE, SPACED APART FROM SAID FIRST REGION: F. INTRODUCING AN IMPURITY DETERMINING THE SAME CONDUCTIVITY TYPE AS THAT OF SAID REGION, THROUGH SAID SECOND AND THIRD HOLES TO FORM RESPECTIVELY SECOND AND THIRD REGIONS HAVING A RELATIVELY HIGH IMPURITY CONCENTRATION: G. REMOVING PART OF THE INSULATING FILMS TO EXPOSE A SURFACE PART OF THE SUBSTRATE BETWEEN SAID FIRST AND THIRD REGIONS AND AN EDGE PART OD THE FIRST REGION, H. FORMING A THIRD INSULATING FILM ON THE EXPOSED SURFACES OF SAID SUBSTRATE AND SAID FIRST REGIONS, AND I. FORMING AN ELECTRODE ON SAID THIRD INSULATING FILM TO EXTEND OVER THE EDGE OF SAID FIRST REGION BUT NOT EXTENDING OVER SAID SECOND REGION.

Claim 2

A METHOD OF MANUFACTURING AN INSULATED GATE TYPE FIELD EFFECT TRANSISTOR, COMPRISING THE STEP OF: A. FORMING A FIRST INSULATING FILM ON A SEMICONDUCOR SUBSTRATE, B. FORMING IN SAID FIRST INSULATING FILM, A FIRST HOLE EXTENDING TO THE SURFACE OF THE SUBSTRATE, C. INTRODUCING A CONDUCTIVE TYPE IMPURITY DETERMINING WHICH IS DIFFERENT FROM THAT OF THE SUBSTRATE, THROUGH SAID FIRST HOLE INTO SAID SUBSTRATE TO FORM A FIRST REGION OF A RELATIVELY LOW IMPURITY CONCENTRATION, D. FORMING A SECOND INSULATING FILM IN SAID HOLE E. FORMING IN SAID FIRST AND SECOND INSULATING FILMS, A SECOND HOLE EXPOSING A SURFACE PORTION OF SAID FIRST REGION, AND A THIRD HOLE EXPOSING A SURFACE PORTION OF SAID SUBSTRATE, SPACED APART FROM SAID FIRST REGION: F. INTRODUCING AN IMPURITY DETERMINING THE SAME CONDUCTIVITY TYPE AS THAT OF SAID REGION, THROUGH SAID SECOND AND THIRD HOLES TO FORM RESPECTIVELY SECOND AND THIRD REGIONS HAVING A RELATIVELY HIGH IMPURITY CONCENTRATION: G. REMOVING PART OF THE INSULATING FILMS TO EXPOSE A SURFACE PART OF THE SUBSTRATE BETWEEN SAID FIRST AND THIRD REGIONS AND AN EDGE PART OD THE FIRST REGION, H. FORMING A THIRD INSULATING FILM ON THE EXPOSED SURFACES OF SAID SUBSTRATE AND SAID FIRST REGIONS, AND I. FORMING AN ELECTRODE ON SAID THIRD INSULATING FILM TO EXTEND OVER THE EDGE OF SAID FIRST REGION BUT NOT EXTENDING OVER SAID SECOND REGION.

Claim 7

A method manufacturing an insulated gate type fiEld effect transistor comprising the steps of: a. forming a first insulating film on a semiconductor substrate; b. forming, in said first insulating film, a first hole extending to the surface of the substrate; c. introducing an impurity determining a conductivity type, which is different from that of the substrate, through said first hole into the substrate to form a first region of a relatively low impurity concentration; d. forming a second insulating film on said first region; e. forming a second and a third hole in said first and second insulating films, so that said second hole exposes part of said first region and said third hole exposes an edge part of the first region, spaced from said second region and a surface part of the substrate in the vicinity of the exposed edge part of the first region; f. forming a third insulating film on the exposed surfaces of said substrate and said first region; g. forming a silicon layer on at least part of said third insulating film to cover the edge of said first region and a surface part of the substrate adjacent to said first region; h. forming, in said insulating films, a fourth hole exposing surface part of said first region, and a fifth hole exposing a surface part of the substrate spaced from said first region, an edge of said fifth hole being registered with an edge of the silicon layer; and i. introducing an impurity determining the same conductivity type as that of said first region, through said fourth and fifth holes to form a second and a third region of a relatively high impurity concentration.

Claim 8

A method manufacturing an insulated gate type fiEld effect transistor comprising the steps of: a. forming a first insulating film on a semiconductor substrate; b. forming, in said first insulating film, a first hole extending to the surface of the substrate; c. introducing an impurity determining a conductivity type, which is different from that of the substrate, through said first hole into the substrate to form a first region of a relatively low impurity concentration; d. forming a second insulating film on said first region; e. forming a second and a third hole in said first and second insulating films, so that said second hole exposes part of said first region and said third hole exposes an edge part of the first region, spaced from said second region and a surface part of the substrate in the vicinity of the exposed edge part of the first region; f. forming a third insulating film on the exposed surfaces of said substrate and said first region; g. forming a silicon layer on at least part of said third insulating film to cover the edge of said first region and a surface part of the substrate adjacent to said first region; h. forming, in said insulating films, a fourth hole exposing surface part of said first region, and a fifth hole exposing a surface part of the substrate spaced from said first region, an edge of said fifth hole being registered with an edge of the silicon layer; and i. introducing an impurity determining the same conductivity type as that of said first region, through said fourth and fifth holes to form a second and a third region of a relatively high impurity concentration.

Claim 9

A method of manufacturing an insulated gate type field effect transistor, comprising the steps of: a. forming an insulating film on a semiconductor substrate; b. forming, in said insulating film, a first and a second hole exposing part of the semiconductor substrate; c. doping the semiconductor surface exposed by said first hole with an impurity determining a conductivity type, different from that of the substrate; d. diffusing the doped impurity into the substrate to form a first region of a relatively low impurity concentration, and e. diffusing an impurity determining the same conductivity type as that of the first region into said first region and said substrate through said first and second holes, to form a second and a third region of relatively high impurity concentration.

Claim 10

A method of manufacturing an insulated gate type field effect transistor, comprising the steps of: a. forming an insulating film on a semiconductor substrate; b. forming, in said insulating film, a first and a second hole exposing part of the semiconductor substrate; c. doping the semiconductor surface exposed by said first hole with an impurity determining a conductivity type, different from that of the substrate; d. diffusing the doped impurity into the substrate to form a first region of a relatively low impurity concentration, and e. diffusing an impurity determining the same conductivity type as that of the first region into said first region and said substrate through said first and second holes, to form a second and a third region of relatively high impurity concentration.

Claim 11

A method of manufacturing a semiconductor device comprising the steps of: a. providing a semiconductor substrate of a first conductivity type; b. selectively introducing an impurity of a second conductivity type, opposite said first conductivity type, into said substrate, to form at least one first semiconductor region of said second conductivity type and having a relatively low impurity concentration therein; c. selectively introducing a second conductivity type impurity into a portion of said at least one first semiconductor region but spaced from the edge thereof, to form at least one second semiconductor region of said second conductivity type and having a relatively high impurity concentration; d. selectively forming an insulating film on a prescribed surface portion of said substrate adjacent said at least one first semiconductor region and overlapping the edge of said first semiconductor region and said substrate but not the edge of said second semiconductor region; and e. forming an electrode layer on said insulating film so that said electrode layer overlaps the edge of said first semiconductor region and said substrate but not the edge of said second semiconductor region.

Claim 12

A method of manufacturing a semiconductor device comprising the steps of: a. providing a semiconductor substrate of a first conductivity type; b. selectively introducing an impurity of a second conductivity type, opposite said first conductivity type, into said substrate, to form at least one first semiconductor region of said second conductivity type and having a relatively low impurity concentration therein; c. selectively introducing a second conductivity type impurity into a portion of said at least one first semiconductor region but spaced from the edge thereof, to form at least one second semiconductor region of said second conductivity type and having a relatively high impurity concentration; d. selectively forming an insulating film on a prescribed surface portion of said substrate adjacent said at least one first semiconductor region and overlapping the edge of said first semiconductor region and said substrate but not the edge of said second semiconductor region; and e. forming an electrode layer on said insulating film so that said electrode layer overlaps the edge of said first semiconductor region and said substrate but not the edge of said second semiconductor region.