Patent US3906255A successfully refreshed from Google Patents.
US3906255A
Expired / Lapsed
US
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MOS current limiting output circuit
Assignee: Motorola Solutions Inc
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Filing: 1974-09-06
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Granted: 1975-09-16
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Expires: 1994-09-06
Abstract
Abstract An MOS push-pull driver circuit includes a pull up MOSFET and a pull-down MOSFET coupled to an output node. A polycrystalline silicon current limiting resistor is connected between the drain of the pull-up MOSFET and the supply voltage conductor to provide a closer tolerance output current than is normally feasible for state-of-the-art MOSFET manufacturing processes.
Inventors
- 👤 Jr William David Mensch
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 20:20
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/096; H03K19/0175; H03K19/0185; H03K19/018507; H03K5/00; H03K5/01; H03K5/02; H03K5/023; H10; H10P; H10P95/00
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
264 words
An MOS circuit comprising: a pull-up MOSFET connected between a first node and an output node and having its gate connected to a second node; a current limiting resistor connected between said first node and a third node for limiting the current in said pull-up MOSFET; a pull-down MOSFET connected between said output node and a fourth node and having its gate connected to a fifth node; a first NOR gate having an output connected to said second node and having one input connected to a sixth node and another input connected to a seventh node; a second NOR gate having an output connected to said fifth node and an input connected to said second node and another input connected to said sixth node; a first inverter having an output connected to said sixth node and an input connected to an eighth node connected to a first input of said MOS circuit; a second inverter having an output connected to said seventh node and an input connected to a ninth node connected to a second input of said MOS circuit; a third inverter having an input connected to said output node and an output connected to a tenth node; a combinational AND/NOR gate having first and second twoinput AND sections, said combinational AND/NOR gate having an output connected to an eleventh node, said first two-input AND section having an input connected to said seventh node and another input connected to an eighth node, said second two-input AND section having an input connected to said sixth node and another input connected to said tenth node.
Claim 2
Dependent Claim
264 words
An MOS circuit comprising: a pull-up MOSFET connected between a first node and an output node and having its gate connected to a second node; a current limiting resistor connected between said first node and a third node for limiting the current in said pull-up MOSFET; a pull-down MOSFET connected between said output node and a fourth node and having its gate connected to a fifth node; a first NOR gate having an output connected to said second node and having one input connected to a sixth node and another input connected to a seventh node; a second NOR gate having an output connected to said fifth node and an input connected to said second node and another input connected to said sixth node; a first inverter having an output connected to said sixth node and an input connected to an eighth node connected to a first input of said MOS circuit; a second inverter having an output connected to said seventh node and an input connected to a ninth node connected to a second input of said MOS circuit; a third inverter having an input connected to said output node and an output connected to a tenth node; a combinational AND/NOR gate having first and second twoinput AND sections, said combinational AND/NOR gate having an output connected to an eleventh node, said first two-input AND section having an input connected to said seventh node and another input connected to an eighth node, said second two-input AND section having an input connected to said sixth node and another input connected to said tenth node.
Claim 3
Dependent Claim
22 words
The MOS circuit as recited in claim 1 further including a pull-up resistor connected between said third node and said second node.
Claim 4
Dependent Claim
19 words
The MOS circuit as recited in claim 2 wherein said first and second NOR gates are bootstrap NOR gates.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-09-15 | 1979-03-17 | 1979-09-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-09-15 | 1983-03-17 | 1983-09-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-09-15 | 1987-03-17 | 1987-09-16 | $7700.00 | Window Closed / Lapsed |