US3839646A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Field effect transistor logic gate with improved noise margins
Assignee: AT&T Inc
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Filing: 1973-08-13
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Granted: 1974-10-01
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Expires: 1993-08-13
Abstract
Abstract The noise margins of a standard field effect transistor logic gate circuit, connected between first and second logic potential terminals, are substantially unequal because the transition region between logic states typically occurs much closer to the more positive of the two potentials. Significant improvement is achieved by detaching the connection to the more positive terminal of the standard logic gate circuit and attaching it to the center tap of a second circuit, comprising a series connection of two additional field effect transistors. The second circuit, connected between the first and second potential terminals, forms a voltage divider and a continuous current path. The respective control electrodes of the two additional transistors are jointly connected to the less positive of the two terminals, causing one of the additional transistors to operate in its triode region and the other to operate in its saturation region. The transition region of the logic gate circuit is thereby narrowed and approximately centered between the two potentials.
Inventors
- 👤 B Soloway
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 05:37
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/003; H03K19/00369; H03K19/00384; H03K19/00346; H03K19/00361; H03K19/02; H03K19/08; H03K19/094; H03K19/0944; H03K19/09441; H03K5/00; H03K5/003
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
107 words
In a logic gate circuit of the type including a data input transistor and a load element connected in series between first and second potential terminals, and an output terminal connected to the common junction between said input transistor and said load element, the improvement comprising a second transistor connected in series between said input transistor and said first terminal, a third transistor connected in parallel with said input transistor and said load element between said second terminal and the common junction of said input and second transistors, and means for connecting respective control electrodes of said second and third transistors jointly to said second potential terminal.
Claim 2
Dependent Claim
107 words
In a logic gate circuit of the type including a data input transistor and a load element connected in series between first and second potential terminals, and an output terminal connected to the common junction between said input transistor and said load element, the improvement comprising a second transistor connected in series between said input transistor and said first terminal, a third transistor connected in parallel with said input transistor and said load element between said second terminal and the common junction of said input and second transistors, and means for connecting respective control electrodes of said second and third transistors jointly to said second potential terminal.
Claim 3
Dependent Claim
122 words
In a logic gate circuit of the type including a data input field effect transistor and a load element field effect transistor connected in series between first and second potential terminals, and an output terminal connected to the common junction between said input transistor and said load element, the improvement comprising a second field effect transistor connected in series between said input transistor and said first terminal, a third field effect transistor connected in parallel with said input transistor and said load element between said second terminal and the common junction of said input and second transistors, means for operating said load element and second transistors each in its triode region, and means for operating said third transistor in its saturation region.
Claim 4
Dependent Claim
122 words
In a logic gate circuit of the type including a data input field effect transistor and a load element field effect transistor connected in series between first and second potential terminals, and an output terminal connected to the common junction between said input transistor and said load element, the improvement comprising a second field effect transistor connected in series between said input transistor and said first terminal, a third field effect transistor connected in parallel with said input transistor and said load element between said second terminal and the common junction of said input and second transistors, means for operating said load element and second transistors each in its triode region, and means for operating said third transistor in its saturation region.
Claim 5
Dependent Claim
99 words
In combination: a first and a second logic potential terminal for connection respectively to a first and a second potential, respectively representing complementary logic states, a third potential terminal, means connected to at least one of said first and second terminals for providing at said third terminal a substantially continuous potential having a predetermined value between said first and second potentials, an input transistor, a load element, means for serially connecting said input transistor and said load element between said second and third potential terminals, an output terminal, and means for connecting said output terminal to said input transistor.
Claim 6
Dependent Claim
99 words
In combination: a first and a second logic potential terminal for connection respectively to a first and a second potential, respectively representing complementary logic states, a third potential terminal, means connected to at least one of said first and second terminals for providing at said third terminal a substantially continuous potential having a predetermined value between said first and second potentials, an input transistor, a load element, means for serially connecting said input transistor and said load element between said second and third potential terminals, an output terminal, and means for connecting said output terminal to said input transistor.
Claim 7
Dependent Claim
48 words
The combination according to claim 3 wherein said providing means comprises potential divider means connected between said first and second potential terminals, said potential divider means having an intermediate potential tap, and means connecting said third potential terminal to said intermediate potential tap of said potential divider means.
Claim 8
Dependent Claim
79 words
The combination according to claim 3 furtheR comprising: a first and a second load, each having at least two terminals, means for connecting one terminal of said first load to said first potential terminal, means for connecting one terminal of said second load to said second potential terminal, means for jointly connecting said other terminal of said first and second loads, and means for connecting said third potential terminal to said joint connection of said first and second loads.
Claim 9
Dependent Claim
45 words
The combination according to claim 5 wherein said first and second loads each comprise a field effect transistor, said combination further comprising: means for operating said first load transistor in its triode region, and means for operating said second load transistor in its saturation region.
Claim 10
Dependent Claim
55 words
The combination according to claim 5 wherein said first and second loads each comprise a field effect transistor, said combination further comprising: means for connecting a control electrode of said first load transistor to said second potential terminal, and means for connecting a control electrode of said second load transistor to said second potential terminal.
Claim 11
Dependent Claim
123 words
In a logic gate circuit of the type having a pair of serially connected transistors interconnected between first and second potential terminals, input means connected to one of said transistors, and output means connected between said pair of transistors, the improvement comprising a third potential terminal; means for connecting said pair of transistors to said first potential terminal through said third potential terminal; said connecting means including two additional transistors, means connecting said two additional transistors in series between said first and second potential terminals, said third potential terminal connected between said additional transistors, means connecting said pair of transistors to said third potential terminal; and means for jointly connecting respective control electrodes of said two additional transistors to said second potential terminal.
Claim 12
Dependent Claim
123 words
In a logic gate circuit of the type having a pair of serially connected transistors interconnected between first and second potential terminals, input means connected to one of said transistors, and output means connected between said pair of transistors, the improvement comprising a third potential terminal; means for connecting said pair of transistors to said first potential terminal through said third potential terminal; said connecting means including two additional transistors, means connecting said two additional transistors in series between said first and second potential terminals, said third potential terminal connected between said additional transistors, means connecting said pair of transistors to said third potential terminal; and means for jointly connecting respective control electrodes of said two additional transistors to said second potential terminal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-09-30 | 1978-04-01 | 1978-10-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-09-30 | 1982-04-01 | 1982-10-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-09-30 | 1986-04-01 | 1986-10-01 | $7700.00 | Window Closed / Lapsed |