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Patent US3899635A successfully refreshed from Google Patents.
US3899635A
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Dual mode deflection synchronizing system
Assignee: RCA Licensing Corp
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Filing: 1974-01-30
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Granted: 1975-08-12
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Expires: 1994-01-30
Abstract
Abstract A dual mode deflection synchronizing system includes a resettable counter which generates noise-free internal synchronizing signals and signals representative of the interval during which external vertical synchronizing signals should be received provided the counter is properly synchronized. A sync signal verification detector is coupled to the source of external vertical sync signals and to a mode switch so that if the external signals arrive during this prediction interval as determined by the sync signal verification detector the system continues to operate in a synchronized mode on its internally generated synchronizing signals. If the external signals do not arrive during this prediction interval, the mode switch switches the system into a non-synchronized mode. A vertical sync signal detector which is also coupled to the source of external sync signals and to the mode switch begins to search for an external signal which has the time duration characteristic of an authentic external synchronizing signal. Until such a signal is received, the system continues to be synchronized by internal synchronizing signals generated by the resettable counter. When such a signal is received, the vertical sync signal detector resets the counter to correct its synchronization with the received external vertical synchronizing signal and toggles the mode switch to return the system to its synchronized mode of operation.
Inventors
- 👤 Steven Alan Steckler
- 👤 Allen Leroy Limberg
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 22:32
CPC Classifications
H; H04; H04N; H04N5/00; H04N5/04; H04N5/12
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
250 words
A synchronizing system comprising: a source of external synchronizing signals; resettable counting means adapted for counting signals from a source of second signals integrally related in frequency to said external signals for generating internal signals at said external synchronizing signal frequency, said resettable counting means capable of being reset by said internal signals; external synchronizing signal verification means coupled to said source of external synchronizing signals and to said resettable counting means for verifying the presence and absence of said external synchronizing signals during said internal signals and for generating first and second signal levels respectively in response thereto; external synchronizing signal detecting means coupled to said source of external synchronizing signals for detecting when signals from said source have at least a predetermined time duration and for generating signals when said time duration is greater than the minimum time duration of said external synchronization signals; and mode switching means coupled to said resettable counting means, to said external synchronizing signal detecting means and to said external synchronizing signal verification means for switching to a non-synchronous mode of operation in response to said second signal level generated by said external synchronizing signal verification means for passing a signal from said external synchronizing signal detecting means upon the occurrence of a subsequent signal from said source of external synchronizing signals for resetting said resettable counting means for synchronizing said internal signals such that succeeding internal signals are substantially in synchronism with said subsequent signal from said source of external synchronizing signals.
Claim 2
Dependent Claim
250 words
A synchronizing system comprising: a source of external synchronizing signals; resettable counting means adapted for counting signals from a source of second signals integrally related in frequency to said external signals for generating internal signals at said external synchronizing signal frequency, said resettable counting means capable of being reset by said internal signals; external synchronizing signal verification means coupled to said source of external synchronizing signals and to said resettable counting means for verifying the presence and absence of said external synchronizing signals during said internal signals and for generating first and second signal levels respectively in response thereto; external synchronizing signal detecting means coupled to said source of external synchronizing signals for detecting when signals from said source have at least a predetermined time duration and for generating signals when said time duration is greater than the minimum time duration of said external synchronization signals; and mode switching means coupled to said resettable counting means, to said external synchronizing signal detecting means and to said external synchronizing signal verification means for switching to a non-synchronous mode of operation in response to said second signal level generated by said external synchronizing signal verification means for passing a signal from said external synchronizing signal detecting means upon the occurrence of a subsequent signal from said source of external synchronizing signals for resetting said resettable counting means for synchronizing said internal signals such that succeeding internal signals are substantially in synchronism with said subsequent signal from said source of external synchronizing signals.
Claim 3
Dependent Claim
89 words
A synchronizing system according to claim 1 wherein: said mode switching means switches from said synchronous mode of operation to said non-synchronous mode of operation immediately upon detecting that said internal signals are not substantially in synchronism with said external synchronizing signals thereby passing said signal generated by said external synchronizing signal detecting means for resetting said resettable counting means and shifting the synchronization of said internal signals such that succeeding internal signals are substantially in synchronism with said next succeeding signal from said source of external synchronizing signals.
Claim 4
Dependent Claim
109 words
A synchronizing system according to claim 1 wherein: said mode switching means switches from said synchronous mode of operation to said non-synchronous mode of operation upon detecting that said internal signals have not been substantially in synchronism with said external synchronizing signals for a predetermined number of cycles of said internal signals, thereby passing said Signal from said external synchronizing signal detecting means for resetting said resettable counting means and shifting the synchronization of said internal signals such that internal signals after said predetermined number of cycles are substantially in synchronism with said next succeeding signal after said predetermined number of cycles from said source of external synchronizing signals.
Claim 5
Dependent Claim
335 words
A synchronizing system comprising: a source of external synchronizing signals; resettable counting means adapted for counting signals from a source of second signals integrally related in frequency to said external signals for generating internal signals at said external synchronizing signal frequency, said resettable counting means capable of being reset by said internal signals; external synchronizing signal verification means comprising: a first coincidence gate, one input terminal of which is coupled through inverting means to said source of external synchronizing signals and another input terminal of which is coupled to said resettable counting means for receiving said internal signals therefrom for generating an absence signal when said external synchronizing signal is absent during said internal signal; weighting means coupled to said resettable counting means for adjusting the amplitude of said internal signal; subtracting and integrating means coupled to said first coincidence gate and to said weighting means for integrating said weighted internal signals and said external synchronizing signal absence signals and subtracting said integrated absence signals from said integrated weighted internal signals, the difference of said integrated signals forming first and second signal levels respectively representative of the presence or absence of said external synchronizing signals; external synchronizing signal detecting means coupled to said source of external synchronizing signals for detecting when signals from said source have at least a predetermined time duration and for generating signals in response to said detection; and mode switching means coupled to said resettable counting means, to said external synchronizing signal detecting means and to said external synchronizing signal verification means for switching to a non-synchronous mode of operation in response to said second signal level generated by said external synchronizing signal verification means for passing a signal from said external synchronizing signal detecting means upon the occurrence of a subsequent signal from said source of external synchronizing signals for resetting said resettable counting means for synchronizing said internal signals such that succeeding internal signals are substantially in synchronism with said subsequent signal from said source of external synchronizing signals.
Claim 6
Dependent Claim
335 words
A synchronizing system comprising: a source of external synchronizing signals; resettable counting means adapted for counting signals from a source of second signals integrally related in frequency to said external signals for generating internal signals at said external synchronizing signal frequency, said resettable counting means capable of being reset by said internal signals; external synchronizing signal verification means comprising: a first coincidence gate, one input terminal of which is coupled through inverting means to said source of external synchronizing signals and another input terminal of which is coupled to said resettable counting means for receiving said internal signals therefrom for generating an absence signal when said external synchronizing signal is absent during said internal signal; weighting means coupled to said resettable counting means for adjusting the amplitude of said internal signal; subtracting and integrating means coupled to said first coincidence gate and to said weighting means for integrating said weighted internal signals and said external synchronizing signal absence signals and subtracting said integrated absence signals from said integrated weighted internal signals, the difference of said integrated signals forming first and second signal levels respectively representative of the presence or absence of said external synchronizing signals; external synchronizing signal detecting means coupled to said source of external synchronizing signals for detecting when signals from said source have at least a predetermined time duration and for generating signals in response to said detection; and mode switching means coupled to said resettable counting means, to said external synchronizing signal detecting means and to said external synchronizing signal verification means for switching to a non-synchronous mode of operation in response to said second signal level generated by said external synchronizing signal verification means for passing a signal from said external synchronizing signal detecting means upon the occurrence of a subsequent signal from said source of external synchronizing signals for resetting said resettable counting means for synchronizing said internal signals such that succeeding internal signals are substantially in synchronism with said subsequent signal from said source of external synchronizing signals.
Claim 7
Dependent Claim
82 words
A synchronizing system according to claim 4 wherein said external synchronizing signal verification means further comprises comparing means coupled to said subtracting and integrating means for comparing the result of said subtraction and integration to a threshold reference voltage for determining whether said external synchronizing signal information occurring during said internal signal is sufficient so that said internal signal may be considered to be substantially in synchronism with said external synchronizing signal and for generating said first signal level in response thereto.
Claim 8
Dependent Claim
122 words
A synchronizing system according to claim 4 wherein said external synchronizing signal verification means further comprises a second coincidence gate, one input terminal of which is coupled to said source of external synchronizing signals and another input terminal of which is coupled to an output terminal of a delay line, the input terminal of which is coupled to said source of external synchronizing signals, and an output terminal of said second coincidence gate is coupled through said inverting means to said input terminal of said first coincidence gate for removing pulses of shorter duRation than the delay time of said delay line from said external synchronizing signal information coupled through said inverting means to said input terminal of said first coincidence gate.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-08-11 | 1979-02-10 | 1979-08-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-08-11 | 1983-02-10 | 1983-08-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-08-11 | 1987-02-10 | 1987-08-12 | $7700.00 | Window Closed / Lapsed |