Synchronous sequential controller for logic outputs

Claim 1

A synchronous sequential controller for issuing a predetermined sequence of instructions, said controller comprising: gating means for sequentially gating starting and other addresses, each of which is associated with a separate instruction; addressing means connected to said gating means for sequentially storing each of said addresses gated by said gating means; decoding means connected to said addressing means for decoding the one of said addresses currently stored in said addressing means and for issuing the instruction associated with that address on a corresponding one of a plurality of separate output lines of said decoding means; address modification means connected to the output lines of said decoding means and to said gating means for directly translating each instruction issued on any of the output lines of said decoding means into the one of said addresses associated with the next instruction in said predetermined sequence to be issued and for transmitting that address to said gating means; clock means connected to said addressing means and to said decoding means for determining the point in time at which each of said instructions is to be issued; and enabling means connected to said gating means and to said decoding means and responsive to said clock means for simultaneously enabling said decoding means and disabling said gating means.