Patent US3886004A successfully refreshed from Google Patents.
US3886004A
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Method of making silicon semiconductor devices utilizing enhanced thermal oxidation
Assignee: Ferranti International PLC
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Filing: 1973-02-27
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Granted: 1975-05-27
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Expires: 1993-02-27
Abstract
Abstract A silicon oxide layer is formed on a phosphorus doped surface region of a silicon semiconductor body by steam treatment, there being an enhanced growth rate of the silicon oxide on the phosphorus doped region enabling, for example, the provision of a low temperature steam treatment, and/or the production, possibly within an aperture in an already provided silicon oxide layer less than 3000A thick, of a thin silicon oxide layer, so that impurity concentration gradients within the semiconductor body are not caused to change by a significant extent and the surface concentration of phosphorus within the region is not significantly depleted.
Inventors
- 👤 Jeffrey Alan Bruchez
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 15:12
CPC Classifications
H; H10; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/012; H10P; H10P14/00; H10P14/60; H10P14/63; H10P14/6302; H10P14/6304; H10P14/6306; H10P14/6308; H10P14/6309; H10P14/6322; H10P95/00; H10W10/10; H10W10/13; Y; Y10; Y10S; Y10S148/00; Y10S148/037; Y10S148/043; Y10S148/051; Y10S148/085; Y10S148/106; Y10S148/116; Y10S148/118; Y10S148/173; Y10S438/00; Y10S438/911; Y10S438/981
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
259 words
AN IMPROVED METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE OF THE COLLECTOR-DIFFUSION-ISOLATION TYPE IN A SEMICONDUCTOR BODY COMPRISES THE STEPS OF PROVIDING A SUBSTRATE OF P CONDUCTIVITY TYPE, FORMING AT LEAST ONE HEAVILY DOPED REGION OF N CONDUCTIVITY TYPE ADJACENT TO A SELECTED PART OF ONE SURFACE OF THE SUBSTRATE, DEPOSITING ON SAID SURFACE AN EXTRINISIC EPITAXIAL LAYER OF SAID P CONDUCTIVITY TYPE THEREBY BURYING SAID HEAVILY DOPED REGION AT THE INTERFACE OF SAID SUBSTRATE AND SAID EPITAXIAL LAYER, FORMING AN ISOLATION BARRIER OF SAID N CONDUCTIVITY TYPE EXTENDING THROUGH SAID EPITAXIAL LAYER AND IN CONTACT WITH THE HEAVILY DOPED BURIED REGION, DEPOSITING A FIRST SILICON OXIDE LAYER ON THE WHOLE OF THE EXPOSED SURFACE OF THE EPITAXIAL LAYER, SELECTIVELY REMOVING PORTIONS OF THE SILICON OXIDE LAYER TO EXPOSE AT LEAST ONE SELECTEDREGION OF THE EPITAXIAL LAYER, SELECTIVELY DOPING SELECTED REGIONS WITH PHOSPHORUS TO FORM A HEAVILY DOPED REGION OF SAID N CONDUCTIVITY TYPE AND CHARACTERIZED BY THE IMPROVEMENT OF LIMITING THE DEPOSITION OF THE FIRST SILICON OXIDE LAYER TO FORM A FIRST OXIDE LAYER HAVIING THICKNESS LESS THAN 3000A THICK, SUBJECTING THE DOPED SELECTED REGIONS TO STEAM OXIDATION TO PROVIDE A SECOND OXIDE LAYER WITHOUT CAUSING A SIGNIFICANT CHANGE IN THE IMPURITY CONCENTRATION GRADIENTS WITHIN THE SEMICONDUCTOR BODY WHEREIN THE THICKNESS OF THE SILICON OXIDE LAYER FORMED BY STEAM OXIDATION OF THE DOPED REGIONS PROVIDES A SMOOTHLY GRADED THICKNESS BETWEEN THE FIRST AND THE SECOND SILICON OXIDE LAYERS AND SIMULTANEOUSLY ETCHING APERTURES THROUGH THE FIRST AND THE SECOND SILICON OXIDE LAYERS TO EXPOSE SURFACE REGIONS OF THE EPITAXIAL LAYER.
Claim 2
Dependent Claim
259 words
AN IMPROVED METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE OF THE COLLECTOR-DIFFUSION-ISOLATION TYPE IN A SEMICONDUCTOR BODY COMPRISES THE STEPS OF PROVIDING A SUBSTRATE OF P CONDUCTIVITY TYPE, FORMING AT LEAST ONE HEAVILY DOPED REGION OF N CONDUCTIVITY TYPE ADJACENT TO A SELECTED PART OF ONE SURFACE OF THE SUBSTRATE, DEPOSITING ON SAID SURFACE AN EXTRINISIC EPITAXIAL LAYER OF SAID P CONDUCTIVITY TYPE THEREBY BURYING SAID HEAVILY DOPED REGION AT THE INTERFACE OF SAID SUBSTRATE AND SAID EPITAXIAL LAYER, FORMING AN ISOLATION BARRIER OF SAID N CONDUCTIVITY TYPE EXTENDING THROUGH SAID EPITAXIAL LAYER AND IN CONTACT WITH THE HEAVILY DOPED BURIED REGION, DEPOSITING A FIRST SILICON OXIDE LAYER ON THE WHOLE OF THE EXPOSED SURFACE OF THE EPITAXIAL LAYER, SELECTIVELY REMOVING PORTIONS OF THE SILICON OXIDE LAYER TO EXPOSE AT LEAST ONE SELECTEDREGION OF THE EPITAXIAL LAYER, SELECTIVELY DOPING SELECTED REGIONS WITH PHOSPHORUS TO FORM A HEAVILY DOPED REGION OF SAID N CONDUCTIVITY TYPE AND CHARACTERIZED BY THE IMPROVEMENT OF LIMITING THE DEPOSITION OF THE FIRST SILICON OXIDE LAYER TO FORM A FIRST OXIDE LAYER HAVIING THICKNESS LESS THAN 3000A THICK, SUBJECTING THE DOPED SELECTED REGIONS TO STEAM OXIDATION TO PROVIDE A SECOND OXIDE LAYER WITHOUT CAUSING A SIGNIFICANT CHANGE IN THE IMPURITY CONCENTRATION GRADIENTS WITHIN THE SEMICONDUCTOR BODY WHEREIN THE THICKNESS OF THE SILICON OXIDE LAYER FORMED BY STEAM OXIDATION OF THE DOPED REGIONS PROVIDES A SMOOTHLY GRADED THICKNESS BETWEEN THE FIRST AND THE SECOND SILICON OXIDE LAYERS AND SIMULTANEOUSLY ETCHING APERTURES THROUGH THE FIRST AND THE SECOND SILICON OXIDE LAYERS TO EXPOSE SURFACE REGIONS OF THE EPITAXIAL LAYER.
Claim 3
Dependent Claim
52 words
Am improved method of manufacturing a semiconductor device as set forth in claim 1 wherein the thickness of the silicon oxide layer formed by steam oxidation of the doped regions is substantially the same as the thickness of the first silicon oxide layer provided on the exposed surface of the epitaxial layer.
Claim 4
Dependent Claim
28 words
A method of manufacturing a semiconductor device as set forth in claim 1 wherein the temperature of the steam treatment is in the range of 700*C to 1100*C.
Claim 5
Dependent Claim
85 words
An improved method of manufacturing a semiconductor device as set forth in claim 1 wherein said heavily doped buried region and said isolation barrier are of the N+ type thereby defining a base of a transistor within the epitaxial layer, said heavily doped buried region and isolation barrier defining the collector of the transistor and said selectively doped regions defining an emitter of the transistor and further including the step of forming contacts in the apertures for the emitter, base and collector of the transistor.
Claim 6
Dependent Claim
275 words
An improved method of manufacturing a semiconductor device of the collector-diffusion-isolation type in a semiconductor body comprises the steps of providing a substrate of P conductivity type, forming a heavily doped region of N conductivity type adjacent to a selected part of one surface of the substrate, depositing on said surface an extrinsic epitaxial layer of said P conductivity type thereby burying said heavily doped region at the interface of said substrate and said epitaxial layer, forming an isolation barrier of said N conductivity type extending through said epitaxial layer and in contact with the heavily doped buried region, doping the whole of the exposed surface of the epitaxial layer by non-selective diffusion of a P type conductivity material, depositing a first silicon oxide layer on the whole of the exposed surface of the epitaxial layer, selectively removing portions of the silicon oxide layer to expose at least one selected region of the surface of the epitaxial layer, selectively doping the selected regions with phosphorus to form heavily doped regions of said N conductivity type and characterized by the improvement of limiting the deposition of the first silicon oxide layer to form a first oxide layer having thickness less than 3000A thick and subjecting the doped selected regions to steam oxidation to provide a second oxide layer without causing a significant change in the impurity concentration gradients within the semiconductor body wherein the thickness of the silicon oxide layer formed by steam oxidation of the doped regions provides a smoothly graded thickness between the first and the second silicon oxide layers and simultaneously etching apertures through both said first and said second silicon oxide layer.
Claim 7
Dependent Claim
275 words
An improved method of manufacturing a semiconductor device of the collector-diffusion-isolation type in a semiconductor body comprises the steps of providing a substrate of P conductivity type, forming a heavily doped region of N conductivity type adjacent to a selected part of one surface of the substrate, depositing on said surface an extrinsic epitaxial layer of said P conductivity type thereby burying said heavily doped region at the interface of said substrate and said epitaxial layer, forming an isolation barrier of said N conductivity type extending through said epitaxial layer and in contact with the heavily doped buried region, doping the whole of the exposed surface of the epitaxial layer by non-selective diffusion of a P type conductivity material, depositing a first silicon oxide layer on the whole of the exposed surface of the epitaxial layer, selectively removing portions of the silicon oxide layer to expose at least one selected region of the surface of the epitaxial layer, selectively doping the selected regions with phosphorus to form heavily doped regions of said N conductivity type and characterized by the improvement of limiting the deposition of the first silicon oxide layer to form a first oxide layer having thickness less than 3000A thick and subjecting the doped selected regions to steam oxidation to provide a second oxide layer without causing a significant change in the impurity concentration gradients within the semiconductor body wherein the thickness of the silicon oxide layer formed by steam oxidation of the doped regions provides a smoothly graded thickness between the first and the second silicon oxide layers and simultaneously etching apertures through both said first and said second silicon oxide layer.
Claim 8
Dependent Claim
52 words
An improved method of manufacturing a semiconductor device as set forth in claim 5 wherein the thickness of the silicon oxide layer formed by steam oxidation of the doped regions is substantially the same as the thickness of the first silicon oxide layer provided on the exposed surface of the epitaxial layer.
Claim 9
Dependent Claim
28 words
A method of manufacturing a semiconductor device as set forth in claim 5 wherein the temperature of the steam treatment is in the range of 700*C to 1100*C.
Claim 10
Dependent Claim
85 words
An improved method of manufacturing a semiconductor device as set forth in claim 5 wherein said heavily doped buried region and said isolation barrier are of the N+ type thereby defining a base of a transistor within the epitaxial layer, said heavily doped buried region and isolation barrier defIning the collector of the transistor and said selectively doped regions defining an emitter of the transistor and further including the step of forming contacts in the apertures for the emitter, base and collector of the transistor.
References Cited (Backward Citations)
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US3404451A
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US3575741A
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US3755014A
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US3717516A
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US3756876A
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-05-26 | 1978-11-25 | 1979-05-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-05-26 | 1982-11-25 | 1983-05-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-05-26 | 1986-11-25 | 1987-05-27 | $7700.00 | Window Closed / Lapsed |