Patent US3878404A successfully refreshed from Google Patents.
US3878404A
Expired / Lapsed
US
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Integrated circuit of the MOS variety
Assignee: Electronic Arrays Inc
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Filing: 1972-10-30
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Granted: 1975-04-15
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Expires: 1992-10-30
Abstract
Abstract A MOSFET read/write random access memory is disclosed in which the individual bit cells perform individually, autonomously but concurrently refresh operation upon application of write pulses. Information can be changed in an addressed cell in a write cycle, and copies from the cell in a read cycle. The cells each are constructed from three MOSFET''s, two nodes and a voltage gated or voltage dependent capacitor. The latter capacitor has just one main electrode and a gate of MOSFET-like configuration. The principle circuit involving that capacitor has the gate of a regulative MOSFET connected to the capacitor gate, both gates are or pertain to a node. A signal on the main electrode is transmitted by the capacitor only when the node is charged and only then is the regular MOSFET rendered conductive. The two other transistors and the additional node in a cell serves as charge transfer and addressing elements.
Inventors
- 👤 Terry R Walther
- 👤 Michael R Mccoy
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 14:51
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/402; H; H10; H10B; H10B12/00; H10D; H10D84/00; H10D84/80; H10D84/811; H10D84/813
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
197 words
In an integrated circuit of the variety, wherein the active elements include field effect transistors, which includes first signal means for providing read control signals and second signals means for receiving signals, and which also includes means providing a driving voltage, independently from the said read control signals, the combination comprising: means for establishing first and second nodes; a first field effect transistor having its main electrodes respectively connected to the first and second nodes, and having a gate for receiving a write-control signal; a second field effect transistor having its main electrodes connected directly to the first node and to the means providing driving voltage to derive therefrom driving voltage independently from the read and write control signals, the second transistor having its gate connected to as being part of the second node; a voltage gated capacitor structurally integral with said transistor and having its gate connected to the second node and its single main electrode connected to the first signal means to receive therefrom a read control signal; and field effect means connected to be responsive to addressing signals for transferring signals between the second node and the second signal means outside of the combination.
Claim 2
Dependent Claim
197 words
In an integrated circuit of the variety, wherein the active elements include field effect transistors, which includes first signal means for providing read control signals and second signals means for receiving signals, and which also includes means providing a driving voltage, independently from the said read control signals, the combination comprising: means for establishing first and second nodes; a first field effect transistor having its main electrodes respectively connected to the first and second nodes, and having a gate for receiving a write-control signal; a second field effect transistor having its main electrodes connected directly to the first node and to the means providing driving voltage to derive therefrom driving voltage independently from the read and write control signals, the second transistor having its gate connected to as being part of the second node; a voltage gated capacitor structurally integral with said transistor and having its gate connected to the second node and its single main electrode connected to the first signal means to receive therefrom a read control signal; and field effect means connected to be responsive to addressing signals for transferring signals between the second node and the second signal means outside of the combination.
Claim 3
Dependent Claim
35 words
In a circuit as in claim 1, including means for providing alternating read and write control signals for periodically restoring a charge of the second node, independently from addressing signals in the field effect means.
Claim 4
Dependent Claim
79 words
In a circuit as in claim 2, the MOS field effect means including a third field effect transistor, the signal means including an input/output line, tHe third field effect transistor connected between the first node and the input/output line, the signal means including means to set a bit into the input/output line concurrently with a write signal on the gate of the first MOS-FET, and means to copy a bit from the input/output line concurrently with a read signal.
Claim 5
Dependent Claim
243 words
An improved three transistor memory cell responsive to alternating and separately provided read and write signals comprising: first and second pairs of access lines, wherein the first pair of access line includes one line receiving permanently bias potential, and one of the second pair of lines receiving an addressing signal independently from the read and write signals, the other one of the second pair of lines receiving the write signals only; first and second field effect transistors having their source-drain paths series connected between the line receiving bias potential and the other one of said first pair of access lines and having a common junction developed as a first node; the gate of said first transistor forming a second storage node for storing information in the form of electric charge; the gate of said second transistor coupled to the one of said second pair of access lines and controlled by the addressing signals thereon; a third field effect transistor, having its gate coupled to the other of said second pair of access lines and controlled by the write signals thereon and having its drain-source connected between the first and second node for coupling signals on said first node to said second storage node; and a voltage variable capacitor, comprising a gate electrode and a drain electrode, connected for receiving and coupling the read signals to said storage node only in dependance upon the charge content of said storage node as biasing the capacitor.
Claim 6
Dependent Claim
243 words
An improved three transistor memory cell responsive to alternating and separately provided read and write signals comprising: first and second pairs of access lines, wherein the first pair of access line includes one line receiving permanently bias potential, and one of the second pair of lines receiving an addressing signal independently from the read and write signals, the other one of the second pair of lines receiving the write signals only; first and second field effect transistors having their source-drain paths series connected between the line receiving bias potential and the other one of said first pair of access lines and having a common junction developed as a first node; the gate of said first transistor forming a second storage node for storing information in the form of electric charge; the gate of said second transistor coupled to the one of said second pair of access lines and controlled by the addressing signals thereon; a third field effect transistor, having its gate coupled to the other of said second pair of access lines and controlled by the write signals thereon and having its drain-source connected between the first and second node for coupling signals on said first node to said second storage node; and a voltage variable capacitor, comprising a gate electrode and a drain electrode, connected for receiving and coupling the read signals to said storage node only in dependance upon the charge content of said storage node as biasing the capacitor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-04-14 | 1978-10-14 | 1979-04-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-04-14 | 1982-10-14 | 1983-04-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-04-14 | 1986-10-14 | 1987-04-15 | $7700.00 | Window Closed / Lapsed |