Logic gate circuit including a Schottky barrier diode

Claim 1

A logic circuit having first and second logic circuits both formed in a single P-type semiconductor substrate; each of said first and second logic circuits comprising an NPN transistor, a plurality of Schottky barrier diodes each connected to said transistor collector terminal, a first impedance element, an input terminal connected to said transistor base, and a plurality of output terminals, an N-type collector region of said NPN transistor being formed in the upper surface of said substrate, an elongated P-type base region of said NPN transistor being formed in said collector region, an N-type emitter region of said NPN transistor being formed at one end of said elongated base region therein, each of said plurality of said Schottky barrier diodes including a metal electrode attached to the surface of said collector region near said one end of said base region, said impedance element being defined by the part of said elongated base region lying between said emitter region and the other end of said elongated base region, said input terminal including an ohmic contact attached to said one end of said elongated base region, a plurality of said output terminals being connected to said respective metal electrodes, and a voltage source connected between said other end of said elongated base region and said emitter region, one of a plurality of said output terminals of said first logic circuit being connected to said input terminal of said second logic circuit.