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US3860831A
Expired / Lapsed
US
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Logic circuit, in particular a decoder, with redundant elements
Assignee: Siemens AG
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Filing: 1972-10-06
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Granted: 1975-01-14
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Expires: 1992-10-06
Abstract
Abstract A logic circuit with a redundant element is particularly characterized in that an associative memory element is additionally provided which is to electronically connect a redundant element with the logic circuit.
Inventors
- 👤 Karl Goser
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 17:27
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/78; G11C29/781; G11C15/00; G11C15/04
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
127 words
A logic device comprising: an output logic circuit; an input logic circuit connected to said output logic circuit for receiving signals corresponding to said output logic circuit; a redundant output logic circuit for replacing said output logic circuit when the latter becomes faulty; and an associative memory element for storing the address of said input logic circuit, said associative memory element connected to said input logic circuit, to said output logic circuit and to said redundant output logic circuit and operable only in response to the operation of said input logic circuit when said address is stored in said associative memory element to inhibit operation of said output logic circuit and effect operation of said redundant output logic circuit as a replacement for said output logic circuit.
Claim 2
Dependent Claim
127 words
A logic device comprising: an output logic circuit; an input logic circuit connected to said output logic circuit for receiving signals corresponding to said output logic circuit; a redundant output logic circuit for replacing said output logic circuit when the latter becomes faulty; and an associative memory element for storing the address of said input logic circuit, said associative memory element connected to said input logic circuit, to said output logic circuit and to said redundant output logic circuit and operable only in response to the operation of said input logic circuit when said address is stored in said associative memory element to inhibit operation of said output logic circuit and effect operation of said redundant output logic circuit as a replacement for said output logic circuit.
Claim 3
Dependent Claim
134 words
A logic decoder comprising: a plurality of output logic circuits each having an address associated therewith; a plurality of input logic circuits connected to and selectively operating said plurality of output logic circuits in response to the receipt of corresponding address signals; a redundant output logic circuit; and an associative memory for storing an address corresponding to a faulty output logic circuit, said associative memory connected to said plurality of output logic circuits, to said plurality of input logic circuits and to said redundant output logic circuit and operable only in response to receipt of an address from said input logic circuits which corresponds to the stored address to inhibit operation of the corresponding output logic circuit and effect operation of said redundant output logic circuit as a replacement for an output logic circuit.
Claim 4
Dependent Claim
134 words
A logic decoder comprising: a plurality of output logic circuits each having an address associated therewith; a plurality of input logic circuits connected to and selectively operating said plurality of output logic circuits in response to the receipt of corresponding address signals; a redundant output logic circuit; and an associative memory for storing an address corresponding to a faulty output logic circuit, said associative memory connected to said plurality of output logic circuits, to said plurality of input logic circuits and to said redundant output logic circuit and operable only in response to receipt of an address from said input logic circuits which corresponds to the stored address to inhibit operation of the corresponding output logic circuit and effect operation of said redundant output logic circuit as a replacement for an output logic circuit.
Claim 5
Dependent Claim
27 words
A decoder according to claim 2, wherein said decoder is a main decoder comprising a plurality of subdecoders each including at least one redundant output logic circuit.
Claim 6
Dependent Claim
30 words
A decoder according to claim 2, wherein said input logic circuits, said output logic circuits, said redundant output logic circuit and said associative memory are constructed as an integrated circuit.
Claim 7
Dependent Claim
15 words
A decoder accordIng to claim 2, wherein said associative memory comprises bistable flip-flop storage circuits.
Claim 8
Dependent Claim
35 words
A decoder according to claim 2, wherein said associative memory comprises a plurality of electrically alterable bistable storage elements each including an input for receiving signals which constitute an address of an output logic circuit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-01-13 | 1978-07-15 | 1979-01-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-01-13 | 1982-07-15 | 1983-01-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-01-13 | 1986-07-15 | 1987-01-14 | $7700.00 | Window Closed / Lapsed |