US3665174A
Expired / Lapsed
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Error tolerant arithmetic logic unit
Assignee: International Business Machines Corp
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Filing: 1968-09-03
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Granted: 1972-05-23
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Expires: 1988-09-03
Abstract
Abstract The error tolerant arithmetic logical unit is divided into vertical bit-planes which are relatively independent, being coupled mainly for the purposes of shifts and carry propagation. The system tolerates failures and still functions correctly by reconfiguring the unit through the control of interplane connections. By inserting a spare bit-plane into the system and switching between bit-planes to bypass a failed plane, the effect of the failed plane or of a failure in a position of control logic can be eliminated.
Inventors
- 👤 Willard G Bouricius
- 👤 William C Carter
- 👤 Keith A Duke
- 👤 John P Roth
- 👤 Peter R Schneider
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 07:46
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/16; G06F11/20; G06F11/202; G06F11/2023; G06F11/2028; G06F11/2025; G06F11/2038; G06F11/2041
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
367 words
An error tolerant arithmetic logical unit comprising a plurality of normally operational vertical logic planes arranged in horizontal sequence to form a multi-bit position unit, each of said logic planes providing a single bit data path and first and second output signals, at least one spare vertical logic plane providing a spare bit path in said sequence, data input means to provide input data for said logic planes, said data input means including data input lines for each said normally operative logic plane and circuit means for directly connecting the data input lines for a logic plane adjacent to said spare logic plane to said spare logic plane, input selection means normally connecting said data input lines to said normally operational logic planes, said input selection means being operative to selectively connect the data input lines for any operational logic plane to one adjacent operational logic plane, control output means to receive the first output signal from the logic plane forming the last bit position for said unit, first output selection means normally connecting said first output signal from each operational logic plane as a control input signal to an adjacent operational logic plane and operating to bypass said spare logic plane, said first output selection means being operative to selectively bypass the first output signal of any logic plane around the next adjacent logic plane to the logic plane adjacent to the bypassed plane and to selectively connect the first output signal from either of the logic planes forming the last two bit positions to said control output means, control input means to provide a control input signal to the logic plane forming the first bit position, data output means including data output lines for each said normally operational logic plane, second output selection means normally connecting said operational logic planes to said data output lines, said second output selection means being operative to selectively connect the data output lines for any operational logic plane to one adjacent logic plane, and control means operable upon failure of one of said operational logic planes to cause said input and first and second output selection means to bypass said failed logic plane and substitute said spare logic plane.
Claim 2
Dependent Claim
367 words
An error tolerant arithmetic logical unit comprising a plurality of normally operational vertical logic planes arranged in horizontal sequence to form a multi-bit position unit, each of said logic planes providing a single bit data path and first and second output signals, at least one spare vertical logic plane providing a spare bit path in said sequence, data input means to provide input data for said logic planes, said data input means including data input lines for each said normally operative logic plane and circuit means for directly connecting the data input lines for a logic plane adjacent to said spare logic plane to said spare logic plane, input selection means normally connecting said data input lines to said normally operational logic planes, said input selection means being operative to selectively connect the data input lines for any operational logic plane to one adjacent operational logic plane, control output means to receive the first output signal from the logic plane forming the last bit position for said unit, first output selection means normally connecting said first output signal from each operational logic plane as a control input signal to an adjacent operational logic plane and operating to bypass said spare logic plane, said first output selection means being operative to selectively bypass the first output signal of any logic plane around the next adjacent logic plane to the logic plane adjacent to the bypassed plane and to selectively connect the first output signal from either of the logic planes forming the last two bit positions to said control output means, control input means to provide a control input signal to the logic plane forming the first bit position, data output means including data output lines for each said normally operational logic plane, second output selection means normally connecting said operational logic planes to said data output lines, said second output selection means being operative to selectively connect the data output lines for any operational logic plane to one adjacent logic plane, and control means operable upon failure of one of said operational logic planes to cause said input and first and second output selection means to bypass said failed logic plane and substitute said spare logic plane.
Claim 3
Dependent Claim
98 words
The error tolerant arithmetic logical unit of claim 1 wherein said input selection means includes a number of input selection units totaling one less than the number of normally operative logic planes, each said input selection unit including at least one circuit formed by a buffering circuit connected to one of said logic planes, and a plurality of selection gates selectively operable to feed said buffering circuit, one of said selection gates being connected to receive input data for said one logic plane and the remaining selection gates being connected to receive input data for adjacent logic planes.
Claim 4
Dependent Claim
106 words
The error tolerant arithmetic logical unit of claim 2 wherein said first output selection means includes a control selection unit for each operational and spare logic plane, each said control selection unit including a gate/buffer circuit formed by a buffer circuit connected to each logic plane and a buffer circuit connected to said control output means, and a plurality of selection gates selectively operable to feed each said buffer circuit, one of said selection gates being connected to receive the first output signal from the preceding logic plane and the remaining selEction gates being connected to receive the control input signals for the preceding logic planes.
Claim 5
Dependent Claim
94 words
The error tolerant arithmetic logical unit of claim 3 wherein said second output selection means includes an output selection unit for each operational logic plane, each said output selection unit including a gate/buffer circuit formed by a buffer circuit connected to each output line, and a plurality of selection gates selectively operable to feed said buffer circuit, one of said selection gates being connected to one of said logic planes to receive the second output signal therefrom and the remaining selection gates being connected to receive the second output signals from adjacent logic planes.
Claim 6
Dependent Claim
42 words
The error tolerant arithmetic logical unit of claim 4 wherein the data input means includes two data input lines for each normally operative logic plane, said input selection unit for each said normally operative logic plane including two of said gate/buffer circuits.
Claim 7
Dependent Claim
80 words
The error tolerant arithmetic logical unit of claim 4 wherein said control means includes a status register means having a bit position for each normally operative logic plane, each said bit position operating to provide a code and complement signal to operate the gating circuits for said input and first and second output selection means, said status register means being operable upon failure of a logic plane to effect substitution of said spare logic plane for the failed logic plane.
Claim 8
Dependent Claim
183 words
The error tolerant arithmetic logical unit of claim 6 which includes first function register means to provide an operational function code to control said logic planes, a second spare function register means, and function register selection means normally operative to pass the function code from said first function register means to said logic planes, said function register selection means including buffer circuit means connected to provide a function code to said logic planes and two selection gates connected to selectively drive each said buffer circuit means, one of said selection gates being connected to receive a function code from said first function register means and the remaining selection gate being connected to receive a function code from said spare function register means, said status register means having a function bit position to provide a code and complement signal to operate the selection gates of said function register selection means, said status register means being operable upon failure of one of said function register means to control the coding of said function bit position to effect substitution of said second spare function register means.
Claim 9
Dependent Claim
261 words
An error tolerant arithmetic logical unit for processing a multi-bit signal, said unit including a plurality of input terminals to which the bits of said signal are applied and a plurality of output terminals from which the bits of the processed signal are supplied, respectively, comprising a plurality of normally operational vertical logic bit-planes (B) arranged in horizontal sequence to form a multi-bit position module, the number of said normally operational bit-planes corresponding with the number of bits of said signal to be processed; at least one spare vertical logic bit-plane for affording a spare bit path in said horizontal sequence, each of said normally operational and spare bit planes including data input and output terminals, and control signal input and output terminals; input selection means for selectively connecting the multi-bit input terminals of said unit with the input terminals of a corresponding number of said bit-planes, respectively; output selection means for selectively connecting the multi-bit output terminals of said unit with the output terminals of a corresponding number of said bit-planes, respectively; bypass selection means for selectively connecting the control output terminal of each bit-plane alternately with the contRol input and control output terminals of the next successive bit-plane, said selection means being normally operable to de-activate said spare bit-plane and to activate said normally operational bit-planes; and means for operating said selection means to de-activate one of said normally operational bit-planes and to substitute said spare bit-plane therefor, thereby to effect conduction of said multi-bit signal through said vertical bit-planes and said control signal through said bit-plane horizontal sequence.
Claim 10
Dependent Claim
261 words
An error tolerant arithmetic logical unit for processing a multi-bit signal, said unit including a plurality of input terminals to which the bits of said signal are applied and a plurality of output terminals from which the bits of the processed signal are supplied, respectively, comprising a plurality of normally operational vertical logic bit-planes (B) arranged in horizontal sequence to form a multi-bit position module, the number of said normally operational bit-planes corresponding with the number of bits of said signal to be processed; at least one spare vertical logic bit-plane for affording a spare bit path in said horizontal sequence, each of said normally operational and spare bit planes including data input and output terminals, and control signal input and output terminals; input selection means for selectively connecting the multi-bit input terminals of said unit with the input terminals of a corresponding number of said bit-planes, respectively; output selection means for selectively connecting the multi-bit output terminals of said unit with the output terminals of a corresponding number of said bit-planes, respectively; bypass selection means for selectively connecting the control output terminal of each bit-plane alternately with the contRol input and control output terminals of the next successive bit-plane, said selection means being normally operable to de-activate said spare bit-plane and to activate said normally operational bit-planes; and means for operating said selection means to de-activate one of said normally operational bit-planes and to substitute said spare bit-plane therefor, thereby to effect conduction of said multi-bit signal through said vertical bit-planes and said control signal through said bit-plane horizontal sequence.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-05-23 | 1975-11-22 | 1976-05-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-05-23 | 1979-11-22 | 1980-05-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-05-23 | 1983-11-22 | 1984-05-23 | $7700.00 | Window Closed / Lapsed |