On-chip auxiliary latch for down-powering array latch decoders

Abstract

Abstract A monolithic semiconductor array of bi-level powered memory cells is provided with a number of on-chip row and column primary latching circuits. The primary latching circuits allow for the down-powering of the on-chip row and column address decoders after a particular chip and a particular storage cell on the chip have been selected by a respective address signal and a set signal. An auxiliary latching circuit, substantially identical to each of the aforesaid primary latching circuits, also is provided on-chip and receives the same set signal as does each primary latching circuit. The primary latching circuits and the auxiliary latching circuit are ''''set'''' substantially simultaneously by the set signal. The setting of the auxiliary latching circuit initiates a signal which downpowers each of the on-chip address decoders. Means are also provided on-chip for resetting each of the selected primary and the auxiliary latching circuits upon the termination of the chip select signal.

Inventors

• 👤 Steven Platt
• 👤 Jehoshua N Pomeranz
• 👤 Dinesh K Tewarson

Bibliographic Details