Monolithic memory system with bi-level powering for reduced power consumption

Claim 2

An intermittently powered true-complement generator circuit comprising means for intermittently applying power to said circuit, two output terminals, and generator means for providing a true-complement output at said output terminals in response to said power application together with a single binary signal bit input, said generator means providing an up binary state output at each of said output terminals in response to the presence or not of the input signal and the non-application of said power.

Claim 3

The true-complement generator circuit of claim 1 wherein said generator means comprises a pair of common emitter transistors, the collector of one being connected to the base of the other whereby one of the transistors must be non-conductive when the other is conductive, the output of one of said transistor being the true output terminal and the output of the other transistor being the complement output terminal, each of said transistors being non-conductive during the non-application of power to provide an up binary state on both the true and complement output terminals and only one of said transistors being selectively rendered conductive when said power is applied to drop the output of said transistor to a down binary state, the selection of the transistor rendered conductive being dependent on state of the binary bit applied to said generator.