Capacitance multiplication network

Claim 2

The combination comprising: first and second transistors of one conductivity type each having an input electrode, an output electrode and a common electrode; means for connecting first and second output loads at the output electrodes of the first and second transistors, respectively; an input terminal; a relatively constant impedance means connected in common at one end to each one of said common electrodes and at the other end to said input terminal for increasing the impedance between the input electrodes of said transistors and said input terminal; first and second capacitors each being connected between the input electrode of a different one of said first and second transistors and a point-of-reference potential; third and fourth transistors connected to the input electrode of the first and second transistors, respectively, for selectively charging said first and second capacitors, respectively, to a first charge condition; and means for applying a control signal at said input terminal, said control signal having a magnitude to render conductive the first or second transistor when its associated capacitor is charged to said first charge conditiOn.

Claim 3

The combination as claimed in claim 1 wherein said relatively constant impedance means is a resistor.

Claim 4

The combination comprising: first and second transistors each having an input electrode, an output electrode and a common electrode; means for connecting first and second output loads at the output electrodes of the first and second transistors, respectively; first and second input terminals; a first resistor connected in circuit between the common electrode of the first transistor and the first input terminal; a second resistor connected in circuit between the common electrode of the second transistor and the second input terminal; a first capacitor connected between the input electrode of the first transistor and a point-of-reference potential; a second capacitor connected between the input electrode of the second transistor and said point-of-reference potential; first and second signal controlled input means connected to the input electrodes of the first and second transistors, respectively, to control the charge on the first and second capacitors, respectively; and means for applying control signals at said first and second input terminals.

Claim 5

The combination comprising: first and second transistors each having an input electrode, an output electrode and a common electrode; means for connecting first and second output loads at the output electrodes of the first and second transistors, respectively; first and second input terminals; a first resistor connected in circuit between the common electrode of the first transistor and the first input terminal; a second resistor connected in circuit between the common electrode of the second transistor and the second input terminal; a first capacitor connected between the input electrode of the first transistor and a point-of-reference potential; a second capacitor connected between the input electrode of the second transistor and said point-of-reference potential; first and second signal controlled input means connected to the input electrodes of the first and second transistors, respectively, to control the charge on the first and second capacitors, respectively; and means for applying control signals at said first and second input terminals.

Claim 6

The combination comprising: a first input terminal; first and second transistors each having an emitter, a collector and a base; means connecting the emitters of the first and second transistors together and by way of a resistor to said first input terminal; third and fourth transistors having their collectors connected to said first input terminal and having their emitters connected to the bases of the first and second transistors, respectively; a first capacitor connected between the base of the first transistor and a point-of-reference potential; a second capacitor connected between the base of the second transistor and said point-of-reference potential; second and third input terminals coupled respectively to the bases of the third and fourth transistors; means for applying bivalued input signals at the second and third input terminals; means for applying a control signal at the first input terminal; and means for connecting first and second output loads at the collectors of the first and second transistors, respectively.

Claim 7

The combination comprising: a first input terminal; first and second transistors each having an emitter, a collector and a base; means connecting the emitters of the first and second transistors together and by way of a resistor to said first input terminal; third and fourth transistors having their collectors connected to said first input terminal and having their emitters connected to the bases of the first and second transistors, respectively; a first capacitor connected between the base of the first transistor and a point-of-reference potential; a second capacitor connected between the base of the second transistor and said point-of-reference potential; second and third input terminals coupled respectively to the bases of the third and fourth transistors; means for applying bivalued input signals at the second and third input terminals; means for applying a control signal at the first input terminal; and means for connecting first and second output loads at the collectors of the first and second transistors, respectively.

Claim 8

The combination comprising: a first input terminal; first and second transistors of one conductivity type each having an emitter, a collector and a base; means for connecting output loads at the collectors of the first and second transistors, respectively; means connecting the emitters of the first and second transistors together and by way of a resistor to said first input terminal; third and fourth transistors of said one conductivity type having their collectors connected to said first input terminal and having their emitters connected to the bases of the first and second transistors, respectively; a first capacitor connected between the base of the first transistor and a point-of-reference potential; a second capacitor connected between the base of the second transistor and said point-of-reference potential; second and third input terminals coupled respectively to the bases of the third and fourth transistors; means for applying bivalued input signals at the second and third input terminals; and means for switching the voltage at the first input terminal between first and second values, the first value being incapable of rendering either one of the first and second transistors conducting, and the second value being sufficient in magnitude to bias one of the first and second transistors in the on condition and to forward bias the collector-base junction of the associated one of the third and fourth transistors.

Claim 9

The combination comprising: a first input terminal; first and second transistors of one conductivity type each having an emitter, a collector and a base; means for connecting output loads at the collectors of the first and second transistors, respectively; means connecting the emitters of the first and second transistors together and by way of a resistor to said first input terminal; third and fourth transistors of said one conductivity type having their collectors connected to said first input terminal and having their emitters connected to the bases of the first and second transistors, respectively; a first capacitor connected between the base of the first transistor and a point-of-reference potential; a second capacitor connected between the base of the second transistor and said point-of-reference potential; second and third input terminals coupled respectively to the bases of the third and fourth transistors; means for applying bivalued input signals at the second and third input terminals; and means for switching the voltage at the first input terminal between first and second values, the first value being incapable of rendering either one of the first and second transistors conducting, and the second value being sufficient in magnitude to bias one of the first and second transistors in the on condition and to forward bias the collector-base junction of the associated one of the third and fourth transistors.

Claim 10

The combination with a flip-flop having first and second input points and corresponding first and second output terminals, the combination of: first and second transistors each having an emitter, a collector and a base; means coupling the collectors of the first and second transistors to different ones of the first and second input points of the flip-flop; an input terminal; means connecting the emitters of the first and second transistors in common, and by way of a common emitter-resistor to said input terminal; third and fourth transistors having their collector electrodes coupled to said input terminal and having their emitters respectively connected to the bases of the first and second transistors; a first capacitor connected between the base of the first transistor and a point-of-reference potential; a second capacitor connected between the base of the second transistor and said point-of-reference potential; and means for applying a control signal at said first input terminal.

Claim 11

The combination with a flip-flop having first and second input points and corresponding first and second output terminals, the combination of: first and second transistors each having an emitter, a collector and a base; means coupling the collectors of the first and second transistors to different ones of the first and second input points of the flip-flop; an input terminal; means connecting the emitters of the first and second transistors in common, and by way of a common emitter-resistor to said input terminal; third and fourth transistors having their collector electrodes coupled to said input terminal and having their emitters respectively connected to the bases of the first and second transistors; a first capacitor connected between the base of the first transistor and a point-of-reference potential; a second capacitor connected between the base of the second transistor and said point-of-reference potential; and means for applying a control signal at said first input terminal.

Claim 12

The combination as claimed in claim 6, wherein the first, second, third and fourth transistors are of the same conductivity type, and including means coupling the first and second output terminals to the bases of different ones of said third and fourth transistors.

Claim 13

The combination as claimed in claim 6, including a second flip-flop having first and second output terminals, and means for coupling the first and second output terminals of said second flip-flop to the bases of different ones of said third and fourth transistors.

Claim 14

A steering arrangement for a flip-flop having first and second input points, said steering arrangement comprising: first and second transistors each having a base, an emitter, and a collector electrode; an input terminal; a relatively constant impedance means connecting the emitter electrodes of the first and second transistors to said input terminal; first capacitor means connected between the base electrode of the first transistor and a point-of-reference potential; second capacitor means connected between the base electrode of the second transistor and said point-of-reference potential; first and second input circuit means coupled at the base electrodes of the first and second transistors, respectively, for selectively charging the first and second capacitor means, respectively, to a first charge condition; means for connecting the collector electrodes of the first and second transistors to the first and second input points of said flip-flop, respectively; and means for applying a signal to said input terminal, said signal having a magnitude to render conductive the first or second transistor when its associated capacitor means is charged to said first charge condition, for causing current to flow from said capacitance through the base-to-emitter path of said transistor and through said relatively constant impedance means into said input terminal; said relatively constant impedance means limiting the current level by presenting to said capacitance an impedance equal in value to the ohmic value of said relatively constant impedance means multiplied by the current gain of the transistor rendered conductive.

Claim 15

A steering arrangement for a flip-flop having first and second input points, said steering arrangement comprising: first and second transistors each having a base, an emitter, and a collector electrode; an input terminal; a relatively constant impedance means connecting the emitter electrodes of the first and second transistors to said input terminal; first capacitor means connected between the base electrode of the first transistor and a point-of-reference potential; second capacitor means connected between the base electrode of the second transistor and said point-of-reference potential; first and second input circuit means coupled at the base electrodes of the first and second transistors, respectively, for selectively charging the first and second capacitor means, respectively, to a first charge condition; means for connecting the collector electrodes of the first and second transistors to the first and second input points of said flip-flop, respectively; and means for applying a signal to said input terminal, said signal having a magnitude to render conductive the first or second transistor when its associated capacitor means is charged to said first charge condition, for causing current to flow from said capacitance through the base-to-emitter path of said transistor and through said relatively constant impedance means into said input terminal; said relatively constant impedance means limiting the current level by presenting to said capacitance an impedance equal in value to the ohmic value of said relatively constant impedance means multiplied by the current gain of the transistor rendered conductive.

Claim 16

The combination as claimed in claim 9 wherein said relatively constant impedance means is a resistor.