Active circuit for delaying transient signals in a television receiver

Claim 2

An active delay circuit for providing from a transient input signal a delayed output signal, comprising: a summing circuit for providing an output signal from a plurality of input component signals; first means for providing to said summing circuit a first input component signal having a transient waveform similar to the transient input signal waveform; and second means effectively defining a resonant RCL circuit responsive to the input signal for concurrently providing to said summing circuit a second input component signal comprising a generally sine wave excursion (a) opposite in polarity to, (b) initiated substantially concurrently with and (c) having a half wavelength period substantially greater than the rise period of said first input component transient signal.

Claim 3

The active delay circuit of claim 1 wherein said summing circuit includes a transistor, and said component signals are applied to the base thereof.

Claim 4

The active delay circuit of claim 1 wherein said first means comprises a transistor, said input signal being applied to the base thereof, said second means being connected to the collector thereof, and said summing circuit being connected to the emitter thereof.

Claim 5

The active delay circuit of claim 1 wherein said second means is connected to be actuated by said first means.

Claim 6

The active delay circuit of claim 1 wherein said second means is arranged to provide a said second input component signal comprising a damped ringing waveform wherein said excursion is followed by a relatively smaller-amplitude half-wave of polarity similar to that of said first input component signal.

Claim 7

The active delay circuit of claim 1 wherein said input signal defines a transition in amplitude level.

Claim 8

The active delay circuit of claim 1 further including means for adjusting said second means to provide a variable, damped ringing second input component signal.

Claim 9

An active delay circuit for deriving from a transient input signal a time delayed output signal with a preshoot characteristic and concurrent increase in the transient steepness, said circuit comprising means for summing a first transient component signal essentially similar to said input signal with a second component signal defining generally a sine wave excursion (a) opposite in polarity to, (b) initiated substantially concurrently with, and (c) having a half wavelength period substantially greater than the rise period of said first input transient component signal to define a time delayed output signal.

Claim 10

An active delay circuit for deriving from a transient input signal a time delayed output signal with a preshoot characteristic and concurrent increase in the transient steepness, said circuit comprising means for summing a first transient component signal essentially similar to said input signal with a second component signal defining generally a sine wave excursion (a) opposite in polarity to, (b) initiated substantially concurrently with, and (c) having a half wavelength period substantially greater than the rise period of said first input transient component signal to define a time delayed output signal.

Claim 11

The active delay circuit of claim 8 further including means for summing the time delayed output signal with another signal, the time delay effected by said delay circuit being preselected to effectively synchronize arrival of said time delayed output signal and said another signal at the matrixing means.

Claim 12

The active delay circuit of claiM 8 wherein said second component signal includes a relatively small-amplitude half-wave following said excursion of polarity similar to that of the first component signal to provide an overshoot characteristic in said time delayed output signal.

Claim 13

An active delay circuit for providing from an input signal having a rapid rise in amplitude level a delayed output signal, comprising: an output transistor; an input transistor having the input signal applied to the base thereof; first resistance means connected between the emitter of the input transistor and the base of the output transistor; a second resistance means connected between the collector of said input transistor and the base of said output transistor; a parallel resonant circuit including (a) third resistance means, (b) a first inductance means, and (c) capacitance means, connected between said collector of the input transistor and the B+ power supply; a fourth resistance means connected between the B+ power supply and the collector of said output transistor; and resistance means connected between the emitter of said output transistor and ground.

Claim 14

An active delay circuit for providing from an input signal having a rapid rise in amplitude level a delayed output signal, comprising: an output transistor; an input transistor having the input signal applied to the base thereof; first resistance means connected between the emitter of the input transistor and the base of the output transistor; a second resistance means connected between the collector of said input transistor and the base of said output transistor; a parallel resonant circuit including (a) third resistance means, (b) a first inductance means, and (c) capacitance means, connected between said collector of the input transistor and the B+ power supply; a fourth resistance means connected between the B+ power supply and the collector of said output transistor; and resistance means connected between the emitter of said output transistor and ground.

Claim 15

The active delay circuit of claim 11 wherein the component values are preselected to critically damp said resonant circuit and thereby prevent ringing.

Claim 16

The active delay circuit of claim 11 wherein the component values are preselected to provide a damped ringing of said resonant circuit.

Claim 17

The active delay circuit of claim 11 wherein said third resistance means comprises a manually adjustable resistance means and the component values are preselected to provide an adjustable damped ringing of said resonant circuit.

Claim 18

The active delay circuit of claim 11 wherein said capacitance means comprises a trap circuit including a series connected capacitance means and second inductance means preselected to resonate at a preselected frequency.