US3786283A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Delay circuit for providing a variable delay characteristic
Assignee: Sansui Electric Co Ltd
•
Filing: 1971-12-29
•
Granted: 1974-01-15
•
Expires: 1991-12-29
Abstract
Abstract A delay circuit consists of a Toulon circuit one branch of which is a reactance circuit having at least one resonance point and one anti-resonance point wherein the resonance and anti-resonance points are chosen to provide a desired delay characteristic.
Inventors
- 👤 H Iida
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 17:09
CPC Classifications
H; H03; H03H; H03H11/00; H03H11/02; H03H11/16; H03H11/20; H03D; H03D3/00; H03D3/001; H03F; H03F3/00; H03F3/189; H03F3/19; H03F3/191; H03F2203/00; H03F2203/45; H03F2203/45621
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
73 words
A delay equalization circuit comprising a Toulon circuit of the type having a series connected reactance circuit branch and resistive circuit branch, an output terminal at the junction of said branches, and means for applying a voltage across said series connected branches, said reactance circuit branch having at least one resonance point and one anti-resonance point wherein said resonance and anti-resonance points are determinative of the frequency characteristic of said delay equalization circuit.
Claim 2
Dependent Claim
73 words
A delay equalization circuit comprising a Toulon circuit of the type having a series connected reactance circuit branch and resistive circuit branch, an output terminal at the junction of said branches, and means for applying a voltage across said series connected branches, said reactance circuit branch having at least one resonance point and one anti-resonance point wherein said resonance and anti-resonance points are determinative of the frequency characteristic of said delay equalization circuit.
Claim 3
Dependent Claim
36 words
A delay equalization circuit as claimed in Claim 1 wherein said reactance circuit branch comprises a first capacitor and a parallel circuit of a second capacitor and an inductance connected in series with said first capacitor.
Claim 4
Dependent Claim
44 words
A delay equalization circuit as claimed in Claim 1 wherein said reactance circuit branch comprises a first capacitor and a plurality of cascaded parallel circuits connected in series with said first capacitor, each of said parallel circuits consisting of a capacitor and an inductance.
Claim 5
Dependent Claim
57 words
A delay equalization circuit as claimed in claim 1 wherein said means for applying a voltage comprises, a transistor having an emitter, a collector and a base, said series connected branches being coupled across said emitter and collector, wherein an input signal is applied to said base and a delayed output signal appears at said output terminal.
Claim 6
Dependent Claim
37 words
A delay equalization circuit as claimed in Claim 4, wherein said reactance circuit branch comprises a first capacitor and a parallel circuit comprised of a second capacitor and an inductor connected in series with said first capacitor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-01-14 | 1977-07-16 | 1978-01-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-01-14 | 1981-07-16 | 1982-01-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-01-14 | 1985-07-16 | 1986-01-15 | $7700.00 | Window Closed / Lapsed |