High voltage power transistor and method for making

Claim 1

In a method of making power transistors, to steps of a. providing a junction wafer of monocrystalline silicon containing in stacked relation an outer collector layer of relatively low resistivity exposed at the bottom major face of said junction wafer, an inner collector layer of relatively high resistivity surmounting said outer collector layer, a base layer surmounting said inner collector layer and defining therewith a base-collector P/N junction, and an array of spaced emitter regions on said base layer and defining with said base layer the top major face of said junction wafer; b. stacking said junction wafer on a silicon carrier wafer with the opposed major faces of said wafers separated by a metallic alloy bonding layer, subjecting the resulting stack to a thermal treatment to form a metallic alloy bond uniting the opposed major faces of the junction wafer and carrier wafer; c. forming, between the emitter regions in the exposed top major face of the junction wafer, a family of grooves having a depth extending part way through said outer collector layer and defining a plurality of mesas in said junction wafer with each of said mesas including a portion of said outer collector layer surmounted by a portion of said inner collector layer topped by a base region and an emitter region; and d. providing a coating of glass passivating material on the sidewalls and bottoms of said grooves and covering the exposed edges of the interfaces between the base and inner collector region in each mesa and the inner collector and outer collector region in each mesa, whEreby said wafer stack may be subdivided into individual transistor bodies at separation faces extending generally normal to the major faces of said wafers along the bottoms of said grooves, said step of providing glass material comprising the substeps of depositing glass frit in said grooves and heating said stack to fuse said glass frit.