Blanking circuit

Claim 2

A blanking circuit comprising a plurality of field effect transistors connected in series between ground and a load connected to a power source, an inverter circuit having an input connected to the gate electrode of one of said plurality of field effect transistors, means to apply an input signal to the gate electrode of a field effect transistor other than said one field effect transistor, means to apply a blanking signal to said gate electrode of said one field effect transistor, means to obtain an output from said load, and an additional field effect transistor connected between the drain electrode of said one field effect transistor and ground, the gate electrode of said additional field effect transistor being connected to the output of said inverter circuit, whereby the level of that part of said output signal which is determined by said blanking signal can be altered.

Claim 3

A blanking circuit comprising: a plurality of output terminals; a plurality of sets of loads connected between a power source line and said output terminals, respectively; a plurality of sets of series connected field effect transistors connected between ground and said output terminals, respectively; means to connect the gate electrode of one field effect transistor in common with the gate electrodes of the corresponding transistors of the other sets; an inverter circuit having an input connected to the gate electrode of one field effect transistor; means to apply input signals to the gate electrode of another field effect transistor connected in series with said one field effect transistor, and the gate electrodes of the corresponding field effect transistors of the other sets, respectively; and means to apply a blanking signal to said gate electrode of said one field effect transistor; wherein a plurality of additional field effect transistors are connected between ground and said output terminals, respectively, the gate electrodes of said additional field effect transistors being connected in common to the output of said inverter circuit.

Claim 4

A blanking circuit comprising: a plurality of output terminals; a plurality of sets of loads connected between a power source line and said output terminals, respectively; a plurality of sets of series connected field effect transistors connected between ground and said output terminals, respectively; means to connect the gate electrode of one field effect transistor in common with the gate electrodes of the corresponding transistors of the other sets; an inverter circuit having an input connected to the gate electrode of one field effect transistor; means to apply input signals to the gate electrode of another field effect transistor connected in series with said one field effect transistor, and the gate electrodes of the corresponding field effect transistors of the other sets, respectively; and means to apply a blanking signal to said gate electrode of said one field effect transistor; wherein a plurality of additional field effect transistors are connected between ground and said output terminals, respectively, the gate electrodes of said additional field effect transistors being connected in common to the output of said inverter circuit.

Claim 5

A blanking circuit as defined in claim 2 wherein said loads each comprise a further field effect transistor.

Claim 6

A blanking circuit formed in the form of a semiconductor integrated circuit comprising: a first and a second field effect transistor connected in series between ground and a load connected to a power source; means for applying an input signal to the gate electrode of the first field effect transistor; means for applying a blanking signal to the gate electrode of said second field effect transistor; an output terminal connected to said load; and selective means including an inverter circuit having an input connected to the gate of said second field effect transistor, and an additional field effect transistor which has its drain electrode connected to said output terminal, and its source electrode connected to ground, said additional field effect transistor being formed so as to be in the non-conductive state continuously in one condition and so as to have the gate electrode connected to the output of said inverter circuit in another condition.

Claim 7

A blanking circuit formed in the form of a semiconductor integrated circuit comprising: a first and a second field effect transistor connected in series between ground and a load connected to a power source; means for applying an input signal to the gate electrode of the first field effect transistor; means for applying a blanking signal to the gate electrode of said second field effect transistor; an output terminal connected to said load; and selective means including an inverter circuit having an input connected to the gate of said second field effect transistor, and an additional field effect transistor which has its drain electrode connected to said output terminal, and its source electrode connected to ground, said additional field effect transistor being formed so as to be in the non-conductive state continuously in one condition and so as to have the gate electrode connected to the output of said inverter circuit in another condition.

Claim 8

A blanking circuit as defined in claim 4 wherein said load is provided in the form of a further field effect transistor having its source electrode connected to the drain electrode of said second field effect transistor and its gate and drain electrodes connected to respective voltage levels of said power source.

Claim 9

A blanking circuit formed in the form of a semiconductor integrated circuit comprising: a first and a second field effect transistor connected in series between ground and a load connected to a power source; means for applying an input signal to the gate electrode of the first field effect transistor; means for applying a blanking signal to the gate electrode of said second field effect transistor; an output terMinal connected to said load; an inverter circuit having an input connected to the gate electrode of said second field effect transistor; and an additional field effect transistor having its drain electrode connected to said output terminal and its source electrode connected to ground by substantially zero impedance means, and having its gate electrode connected to an output of said inverter circuit.

Claim 10

A blanking circuit formed in the form of a semiconductor integrated circuit comprising: a first and a second field effect transistor connected in series between ground and a load connected to a power source; means for applying an input signal to the gate electrode of the first field effect transistor; means for applying a blanking signal to the gate electrode of said second field effect transistor; an output terMinal connected to said load; an inverter circuit having an input connected to the gate electrode of said second field effect transistor; and an additional field effect transistor having its drain electrode connected to said output terminal and its source electrode connected to ground by substantially zero impedance means, and having its gate electrode connected to an output of said inverter circuit.

Claim 11

A blanking circuit as defined in claim 6 wherein said load is provided in the form of a further field effect transistor having its source electrode connected to the drain electrode of said second field effect transistor and its gate and drain electrodes connected to respective voltage levels of said power source.

Claim 12

A blanking circuit as defined in claim 7 further comprising an additional inverter circuit having its input connected to said output terminal.

Claim 13

A blanking circuit as defined in claim 8 wherein said additional inverter circuit is formed by a pair of series connected field effect transistors connected between ground and said power source.

Claim 14

An integrated circuit comprising: an output line; a power source line; a ground line; a first and a second insulated gate field effect transistor connected in series with each other and each having a relatively thin gate insulator and a gate electrode formed on the insulator, the series connected first and second transistors being connected between said output line and the ground line; a third insulated gate field effect transistor having a relatively thick gate insulator and a gate electrode formed on the insulator, the third transistor being connected between the output line and the ground line; a load connected between the power source line and the output line; and an inverter circuit having an input connected to the gate electrode of said first transistor and an output connected to the gate electrode of said third transistor.

Claim 15

An integrated circuit comprising: an output line; a power source line; a ground line; a first and a second insulated gate field effect transistor connected in series with each other and each having a relatively thin gate insulator and a gate electrode formed on the insulator, the series connected first and second transistors being connected between said output line and the ground line; a third insulated gate field effect transistor having a relatively thick gate insulator and a gate electrode formed on the insulator, the third transistor being connected between the output line and the ground line; a load connected between the power source line and the output line; and an inverter circuit having an input connected to the gate electrode of said first transistor and an output connected to the gate electrode of said third transistor.

Claim 16

An integrated circuit comprising: an output line; a ground line; a first, a second and a third insulated gate field effect transistor, said first and second transistors being connected in series between said output and ground lines, said third transistor being arranged between said output and ground lines; an inverter circuit having an input connected to the gate of the first transistor; and means for inactivating said third transistor whereby avoiding the third transistor from operating in accordance with an output of the inverter circuit.

Claim 17

An integrated circuit comprising: an output line; a ground line; a first, a second and a third insulated gate field effect transistor, said first and second transistors being connected in series between said output and ground lines, said third transistor being arranged between said output and ground lines; an inverter circuit having an input connected to the gate of the first transistor; and means for inactivating said third transistor whereby avoiding the third transistor from operating in accordance with an output of the inverter circuit.