Ripple free counter

Claim 2

A binary counter comprising a counting signal source, a first stage and a plurality of cascaded stages, the output of each stage being connected to the input of the immediately succeeding stage, the input of the first stage being connected to an energy source, means for simultaneously applying said counting signal to all stages, each cascaded stage comprising a first store operative in first and second opposite states, a second store connected to said stage output and operative in first and second opposite states, means jointly responsive to said counting signal and said stage first store being in its first state for connecting said stage input to said stage output to energize said stage second store to its first state from said energy source through all preceding stages when all preceding stage first stores are in their first states, means jointly responsive to said counting signal and said stage first store being in its second state for placing said stage second store in its second state, and means operative upon termination of said counting signal and responsive to the immediately preceding stage second store being in its first state for placing said stage first store in a state opposite to the state of said stage second store.

Claim 3

A binary counter circuit comprising a signal source, a charging voltage source, a reference voltage source, first and second storage capacitors each having first and second terminals and each operative in first and second states, each storage capacitor second terminal being connected to said reFerence voltage source, first switching means jointly responsive to said signal and said first storage capacitor being in its first state for charging said second storage capacitor to its first state, second switching means jointly responsive to said signal and said first storage capacitor being in its second state for putting said second storage capacitor in its second state, and apparatus operative upon termination of said signal comprising third switching means responsive to said second storage capacitor being in its first state for putting said first storage capcitor in its second state, and fourth switching means responsive to said second storage capacitor being in its second state for putting said first storage capacitor in its first state, said first switching means comprising first and second semiconductor devices each having first, second and control electrodes; said first semiconductor device first electrode being connected to said charging voltage source, said first semiconductor device second electrode being connected to said second semiconductor device first electrode, said first semiconductor device control electrode being directly connected to said first storage capacitor first terminal, said second semiconductor device second electrode being connected to said second storage capacitor first terminal, and said second semiconductor device control electrode being connected to said signal source.

Claim 4

A binary counter circuit comprising a signal source, a charging voltage source, a reference voltage source, first and second storage capacitors each having first and second terminals and each operative in first and second states, each storage capacitor second terminal being connected to said reFerence voltage source, first switching means jointly responsive to said signal and said first storage capacitor being in its first state for charging said second storage capacitor to its first state, second switching means jointly responsive to said signal and said first storage capacitor being in its second state for putting said second storage capacitor in its second state, and apparatus operative upon termination of said signal comprising third switching means responsive to said second storage capacitor being in its first state for putting said first storage capcitor in its second state, and fourth switching means responsive to said second storage capacitor being in its second state for putting said first storage capacitor in its first state, said first switching means comprising first and second semiconductor devices each having first, second and control electrodes; said first semiconductor device first electrode being connected to said charging voltage source, said first semiconductor device second electrode being connected to said second semiconductor device first electrode, said first semiconductor device control electrode being directly connected to said first storage capacitor first terminal, said second semiconductor device second electrode being connected to said second storage capacitor first terminal, and said second semiconductor device control electrode being connected to said signal source.

Claim 5

A binary counter circuit according to claim 2 wherein said second switching means comprises a third semiconductor device having first, second and control electrodes, said third semiconductor device first electrode being connected to said second semiconductor device first electrode, said third semiconductor device second electrode being connected to said reference voltage source, and said third semiconductor device control electrode being connected to said first storage capacitor first terminal.

Claim 6

A binary counter circuit according to claim 3 wherein said third switching means comprises fourth and fifth semiconductor devices, each having first, second and control electrodes, said fourth semiconductor device first and control electrodes being connected to said voltage source, said fourth semiconductor device second electrode being connected to said fifth semiconductor device first electrode, said fifth semiconductor device second electrode being connected to said first storage capacitor first terminal, the control electrodes of said fifth semiconductor device being connected to said signal source.

Claim 7

A binary counter circuit according to claim 4 wherein said fourth switching means comprises a sixth semiconductor device having first, second and control electrodes, said sixth semiconductor device first electrode being connected to said fourth semiconductor second electrode and to said fifth semiconductor device first electrode, said sixth semiconductor device second electrode being connected to said reference potential source and said sixth semiconductor device control electrode being connected to said second storage capacitor first terminal.

Claim 8

A binary counter circuit according to claim 5 wherein each semiconductor device comprises an insulated gate field effect transistor having source, drain and gate electrodes, said drain electrode being said semiconductor device first terminal, said source electrode being said semiconductor device second electrode and said gate electrode being said semiconductor device control electrode.

Claim 9

A binary counter circuit comprising a counting signal source, a first stage and at least one cascaded stage each having an input and an output, the output of each stage being connected to the input of the immediately succeeding stage, the input of the first stage being connected to an energy source, each stage including first and second stores operative in first and second states, said second store being connected to said stage output, means jointly responsive to said signal and the first store of said stage being in its first state for cOnnecting said stage input to said stage output for energizing said stage second store to its first state from said energy source through the preceding stages when all preceding stage first stores are in their first states, means responsive to said stage first store being in said second state for placing said stage second store in its second state, and each cascaded stage comprising apparatus operative upon termination of said signal comprising means responsive to the immediately preceding stage second store and said stage second store being in their first states for placing said stage first store in its second state and means responsive to the immediately preceding stage second store being in its first state and said stage second store being in its second state for placing said stage first store in its first state.

Claim 10

A binary counter circuit comprising a counting signal source, a first stage and at least one cascaded stage each having an input and an output, the output of each stage being connected to the input of the immediately succeeding stage, the input of the first stage being connected to an energy source, each stage including first and second stores operative in first and second states, said second store being connected to said stage output, means jointly responsive to said signal and the first store of said stage being in its first state for cOnnecting said stage input to said stage output for energizing said stage second store to its first state from said energy source through the preceding stages when all preceding stage first stores are in their first states, means responsive to said stage first store being in said second state for placing said stage second store in its second state, and each cascaded stage comprising apparatus operative upon termination of said signal comprising means responsive to the immediately preceding stage second store and said stage second store being in their first states for placing said stage first store in its second state and means responsive to the immediately preceding stage second store being in its first state and said stage second store being in its second state for placing said stage first store in its first state.

Claim 11

A binary counter comprising a signal source, a plurality of cascaded states, means for applying said signal from said source to all stages at the same time, each stage including first and second storage capacitors having first and second terminals and operative in first and second states, first switching means jointly responsive to said signal and the first storage capacitor of said stage and all preceding stages being in their first states for placing said second storage device of the stage in its first state, second switching means jointly responsive to said signal and the first storage capacitor of said stage being in its second state for placing said stage second storage capacitor in its second state, and apparatus operative upon termination of said signal comprising third switching means jointly responsive to the immediately preceding stage second storage capacitor being in its first state and said stage second storage capacitor being in its first state for placing said stage first storage capacitor in said second state, and fourth switching means jointly responsive to the immediately preceding stage second storage capacitor being in its first state and said stage second storage capacitor being in its second state for placing said stage first storage capacitor in its first state, and means for resetting each stage to an initial state including means for generating a reset signal, means for applying said reset signal to each second storage capacitor second terminal in the absence of said source signal, each fourth switching means being responsive to the reset signal applied to the second storage capacitor of its stage to unconditionally place the first storage capacitor of its stage in its second state.

Claim 12

A binary counter comprising a signal source, a plurality of cascaded states, means for applying said signal from said source to all stages at the same time, each stage including first and second storage capacitors having first and second terminals and operative in first and second states, first switching means jointly responsive to said signal and the first storage capacitor of said stage and all preceding stages being in their first states for placing said second storage device of the stage in its first state, second switching means jointly responsive to said signal and the first storage capacitor of said stage being in its second state for placing said stage second storage capacitor in its second state, and apparatus operative upon termination of said signal comprising third switching means jointly responsive to the immediately preceding stage second storage capacitor being in its first state and said stage second storage capacitor being in its first state for placing said stage first storage capacitor in said second state, and fourth switching means jointly responsive to the immediately preceding stage second storage capacitor being in its first state and said stage second storage capacitor being in its second state for placing said stage first storage capacitor in its first state, and means for resetting each stage to an initial state including means for generating a reset signal, means for applying said reset signal to each second storage capacitor second terminal in the absence of said source signal, each fourth switching means being responsive to the reset signal applied to the second storage capacitor of its stage to unconditionally place the first storage capacitor of its stage in its second state.

Claim 13

A binary counter comprising a signal source, a plurality of cascaded stages, means for applying said signal from said source to all stages at the same time, each stage including first and second storage capacitors having first and second terminals and operative in first and second states, first switching means jointly responsive to said signal and the first storage capacitor of said stage and all preceding stages being in their first states for placing said second storage device of the stage in its first state, second switching means jointly responsive to said signal and the first storage capacitor of said stage being in its second state for placing said stage second storage capacitor in its second state, and apparatus operative upon termination of said signal comprising third switching means jointly responsive to the immediately preceding stage second storage capacitor being in its first state and said stage second storage capacitor being in its first state for placing said stage first storage capacitor in said second state, and fourth switching means jointly responsive to the immediately preceding stage second storage capacitor being in its first state and said stage second storage capacitor being in its second state for placing said stage first storage capacitor in its first state, and means for resetting each stage to an initial state including means for generating a reset signal, means for applying said reset signal to each first storage capacItor second terminal, each stage second switching means being jointly responsive to said source signal and said reset signal being applied to said stage first storage capacitor to unconditionally place said stage second storage capacitor in its first state.

Claim 14

A binary counter comprising a signal source, a plurality of cascaded stages, means for applying said signal from said source to all stages at the same time, each stage including first and second storage capacitors having first and second terminals and operative in first and second states, first switching means jointly responsive to said signal and the first storage capacitor of said stage and all preceding stages being in their first states for placing said second storage device of the stage in its first state, second switching means jointly responsive to said signal and the first storage capacitor of said stage being in its second state for placing said stage second storage capacitor in its second state, and apparatus operative upon termination of said signal comprising third switching means jointly responsive to the immediately preceding stage second storage capacitor being in its first state and said stage second storage capacitor being in its first state for placing said stage first storage capacitor in said second state, and fourth switching means jointly responsive to the immediately preceding stage second storage capacitor being in its first state and said stage second storage capacitor being in its second state for placing said stage first storage capacitor in its first state, and means for resetting each stage to an initial state including means for generating a reset signal, means for applying said reset signal to each first storage capacItor second terminal, each stage second switching means being jointly responsive to said source signal and said reset signal being applied to said stage first storage capacitor to unconditionally place said stage second storage capacitor in its first state.

Claim 15

A binary counter comprising an input stage and a plurality of stages each having an input and an output, the input of each of said plurality of stages being connected to the output of the immediately preceding stage, the input of said output stage being connected to a first signal source, a second signal source, means for applying said second signal to each stage at the same time; each of said plurality of stages comprising a first storage device operative in first and second states, a second storage device connected to said output and operative in first and second states, first switching means connected between said input and said output jointly responsive to said second signal and the stage first storage device being in its first state for connecting said stage input to said stage output, said first signal being applied through the first switching means of all preceding stages and said stage to said stage second storage device to place said stage second storage device in its first state when said stage and all preceding stage first storage devices are in their first states, second switching means jointly responsive to said second signal and said stage first storage device being in its second state for placing said stage second storage device in its second state, apparatus operative upon termination of said second signal comprising third switching means jointly responsive to the immediately preceding stage second storage device being in its first state and said stage second storage device being in its first state for placing said stage first storage device in its second state, and fourth switching means jointly responsive to said immediately preceding stage second storage device being in its first state and said stage second storage device being in its second state for placing said stage first storage device in its first state.

Claim 16

A binary counter comprising an input stage and a plurality of stages each having an input and an output, the input of each of said plurality of stages being connected to the output of the immediately preceding stage, the input of said output stage being connected to a first signal source, a second signal source, means for applying said second signal to each stage at the same time; each of said plurality of stages comprising a first storage device operative in first and second states, a second storage device connected to said output and operative in first and second states, first switching means connected between said input and said output jointly responsive to said second signal and the stage first storage device being in its first state for connecting said stage input to said stage output, said first signal being applied through the first switching means of all preceding stages and said stage to said stage second storage device to place said stage second storage device in its first state when said stage and all preceding stage first storage devices are in their first states, second switching means jointly responsive to said second signal and said stage first storage device being in its second state for placing said stage second storage device in its second state, apparatus operative upon termination of said second signal comprising third switching means jointly responsive to the immediately preceding stage second storage device being in its first state and said stage second storage device being in its first state for placing said stage first storage device in its second state, and fourth switching means jointly responsive to said immediately preceding stage second storage device being in its first state and said stage second storage device being in its second state for placing said stage first storage device in its first state.

Claim 17

A binary counter according to claim 10 wherein said input stage comprises first and second storage devices operative in first and second states, first switching means jointly responsive to said second signal and said input stage first storage device being in its first state for applying said first signal to said input stage second storage device to place said input stage second storage device in its first state, second switching means jointly responsive to said second signal and said input stage first storage device being in its second state for placing said input stage second storage device in its second state, and apparatus operative upon termination of said second signal comprising third switching means responsive to said input stage second storage device being in its first state for placing said input stage first storage device in its second state and means responsive to said input stage second storage device being in its second state for placing said input stage first storage device in its first state.

Claim 18

A binary counter according to claim 11 wherein each first storage device comprises a storage capacitor having first and second terminals, and each second storage device comprises a storage capacitor having first and second terminals.

Claim 19

A binary counter according to claim 12 wherein each first switching means comprises first and second semiconductor devices each having first, second and control electrodes and a noninverting amplifier having an input and an output, each stage first semiconductor device first electrode being connected to its stage input, each stage first semiconductor device second electrode being connected to its stage amplifier input, each stage first semiconductor device control electrode being connected to its stage first storage capacitor first terminal, each stage second semiconductor device first electrode being connected to its stage amplifier outPut, each stage second semiconductor device second electrode being connected to its stage output and to said stage second storage capacitor first terminal, and each stage second semiconductor device control electrode being connected to said second signal applying means.

Claim 20

A binary counter according to claim 13 wherein each second switching means comprises third and fourth semiconductor devices each having first, second and control electrodes, first resistive means having first and second terminals, a positive voltage source and a reference voltage source, said first resistive means first terminal being connected to said positive voltage source, said third semiconductor device first electrode being connected to its stage first resistive means second terminal, said third semiconductor device second electrode being connected to said reference voltage source, said stage third semiconductor device control electrode being connected to its stage first storage capacitor first terminal, said stage fourth semiconductor device first electrode being connected to its stage amplifier output, said stage fourth semiconductor device second electrode being connected to said reference voltage source, said stage fourth semiconductor device control electrode being connected to its stage third semiconductor device first electrode.

Claim 21

A binary counter according to claim 14 wherein said third switching means comprises a fifth semiconductor device having first, second and control electrodes and second resistive means having first and second terminals, said second resistive means first terminal being connected to said positive voltage source, said fifth semiconductor device first electrode being connected to its stage resistive means second electrode, said fifth semiconductor device second electrode being connected to its stage first storage capacitor first terminal, one control electrode of said fifth semiconductor device being connected to said signal applying means, another control electrode of said fifth semiconductor device except said first stage fifth semiconductor device being connected to the output of the immediately preceding stage, the other control electrode of the first stage fifth semiconductor device being connected to said second signal applying means.

Claim 22

A binary counter according to claim 15 wherein each fourth switching means comprises a sixth semiconductor device having first, second and control electrodes, said sixth semiconductor device first electrode being connected to its stage second resistive means second terminal, said sixth semiconductor device second electrode being connected to said reference voltage source, and said sixth semiconductor device control electrode being connected to its stage second storage capacitor first terminal.

Claim 23

A binary counter according to claim 16 wherein each semiconductor device comprises an insulated gate field effect transistor having source, gate and drain electrodes, said drain electrode corresponding to said semiconductor device first electrode, said source electrode corresponding to said semiconductor device second electrode and said gate electrode corresponding to said semiconductor device control electrode.

Claim 24

A binary counter according to claim 17 wherein all insulated gate field effect transistors are of one conductivity type.

Claim 25

A binary counter according to claim 17 wherein each of the second terminals of all first and second storage capacitors are connected to said reference voltage source.

Claim 26

A binary counter according to claim 17 further comprising means for resetting each stage to an initial state including means for generating a reset signal, means for applying said reset signal to each stage second storage capacitor second terminal in the absence of said second signal, each stage fourth switching means being responsive to said reset signal applied to the second storage capacitor of its stage to unconditionally place the first storage capacitor of its stage in its second state, and the second terminal of Each first stoage capacitor being connected to said reference voltage source.

Claim 27

A binary counter according to claim 17 further comprising means for resetting each stage to an initial state including means for generating a reset signal, means for applying said reset signal to each stage first storage capacitor second terminal, each stage second switching means being jointly responsive to said second signal and said reset signal applied to said stage first storage capacitor second terminal to unconditionally place said stage second storage capacitor in its first state, and the second terminal of each second storage capacitor being connected to said reference voltage source.

Claim 28

A counter comprising a first stage and a plurality of cascaded stages, each stage having an input and an output, a signal source, a charging voltage source, means for applying the signal from said source to all stages at the same time, the output of each stage being connected to the input of the immediately succeeding stage, the input of said first stage being connected to said charging voltage source, each stage comprising first and second storage capacitors operative in first and second states, said second storage capacitor being connected to its stage output, means jointly responsive to said signal and said stage first storage capacitor being in its first state for connecting said stage input to said stage output, said stage second storage capacitor being charged to its first state by said charging voltage source through all preceding stages only when said stage first storage capacitor and all preceding stage first storage capacitors are in their first states, means responsive to said signal for switching said stage second storage capacitor to its second state only when said stage first storage capacitor is in its second state, apparatus operative upon termination of said signal including means responsive to the immediately preceding stage second storage capacitor and said stage second storage capacitor being in third first states for switching said stage first storage capacitor to its second state, and means responsive to the immediately preceding stage second storage capacitor being in its first state and said stage second storage capacitor being in its second state for switching said stage first storage capacitor to its first state.

Claim 29

A counter comprising a first stage and a plurality of cascaded stages, each stage having an input and an output, a signal source, a charging voltage source, means for applying the signal from said source to all stages at the same time, the output of each stage being connected to the input of the immediately succeeding stage, the input of said first stage being connected to said charging voltage source, each stage comprising first and second storage capacitors operative in first and second states, said second storage capacitor being connected to its stage output, means jointly responsive to said signal and said stage first storage capacitor being in its first state for connecting said stage input to said stage output, said stage second storage capacitor being charged to its first state by said charging voltage source through all preceding stages only when said stage first storage capacitor and all preceding stage first storage capacitors are in their first states, means responsive to said signal for switching said stage second storage capacitor to its second state only when said stage first storage capacitor is in its second state, apparatus operative upon termination of said signal including means responsive to the immediately preceding stage second storage capacitor and said stage second storage capacitor being in third first states for switching said stage first storage capacitor to its second state, and means responsive to the immediately preceding stage second storage capacitor being in its first state and said stage second storage capacitor being in its second state for switching said stage first storage capacitor to its first state.

Claim 30

A counter comprising a plurality of cascaded stages and an input stage, an energy source, the output of each stage being connected to the input of the immediately succeeding stage, the input of said first stage being connected to said energy source, a source of signals, means responsive to said signal from said source for applying first and second successively occurring pulses to all stages, each stage comprising a first store operative in first and second states, a second store connected to its stage output and operative in first and second states, first means jointly responsive to said first pulse and said stage first store being in its first state for connecting said stage input to said stage output for energizing said stage second store to its first state from said energy source through the cascaded first means of all preceding stages when all preceding stage first stores and said stage first store are in their first states, means jointly responsive to said second pulse and said stage second store being in its first state and the immediately preceding stage second store being in its first state for placing said stage first store in its second state, means jointly responsive to said second pulse and said stage second store being in its second state and the immediately preceding stage second store being in its first state for placing said stage first store in its first state, and means jointly responsive to said first pulse and to the input stage first store being in its second state for placing all stage second stores in their second states.

Claim 31

A counter comprising a plurality of cascaded stages and an input stage, an energy source, the output of each stage being connected to the input of the immediately succeeding stage, the input of said first stage being connected to said energy source, a source of signals, means responsive to said signal from said source for applying first and second successively occurring pulses to all stages, each stage comprising a first store operative in first and second states, a second store connected to its stage output and operative in first and second states, first means jointly responsive to said first pulse and said stage first store being in its first state for connecting said stage input to said stage output for energizing said stage second store to its first state from said energy source through the cascaded first means of all preceding stages when all preceding stage first stores and said stage first store are in their first states, means jointly responsive to said second pulse and said stage second store being in its first state and the immediately preceding stage second store being in its first state for placing said stage first store in its second state, means jointly responsive to said second pulse and said stage second store being in its second state and the immediately preceding stage second store being in its first state for placing said stage first store in its first state, and means jointly responsive to said first pulse and to the input stage first store being in its second state for placing all stage second stores in their second states.

Claim 32

A counter comprising a first stage and a plurality of cascaded stages, each having an input and aN output, the output of each stage being connected to the input of the immediately succeeding stage, a source of signals to be counted, means responsive to each signal to be counted for generating first, second and third pulses, each stage comprising first and second stores operative in first and second states, first means jointly responsive to said first pulse and the first store of said stage and all preceding stage first stores being in their first states for placing said stage second store in its first state, second means jointly responsive to said second pulse and said stage second store being in its first state and the immediately preceding stage second store being in its first state for placing said stage first store in its second state, third means jointly responsive to said second pulse and said stage second store being in its second state and the immediately preceding state second store being in its first state for placing said stage first store in its first state, and means responsive to said third pulse for placing the second stores of all stages in their second states.

Claim 33

A counter comprising a first stage and a plurality of cascaded stages, each having an input and aN output, the output of each stage being connected to the input of the immediately succeeding stage, a source of signals to be counted, means responsive to each signal to be counted for generating first, second and third pulses, each stage comprising first and second stores operative in first and second states, first means jointly responsive to said first pulse and the first store of said stage and all preceding stage first stores being in their first states for placing said stage second store in its first state, second means jointly responsive to said second pulse and said stage second store being in its first state and the immediately preceding stage second store being in its first state for placing said stage first store in its second state, third means jointly responsive to said second pulse and said stage second store being in its second state and the immediately preceding state second store being in its first state for placing said stage first store in its first state, and means responsive to said third pulse for placing the second stores of all stages in their second states.

Claim 34

A binary counter comprising an energy source, a counting signal source, and first and second stages each comprising an input and an output, first and second stores operative in first and second opposite states, said second store being connected to said stage output, said first stage input being connected to said energy source, said first stage output being connected to said second stage input, means for simultaneously applying said counting signal to said first and second stages, said first stage further comprising means jointly responsive to said counting signal and said first store being in its first state for connecting said first stage input to said first stage output to energize said first stage second store to its first state, second means jointly responsive to said counting signal and said first stage first store being in its second state for placing said first stage second store in its second state, apparatus operative upon termination of said counting signal comprising third means responsive to the state of said first stage second store for placing said first stage first store in a state opposite to the state of the first stage second store, said second stage further comprising means jointly responsive to said counting signal and said second stage first store being in its first state for connecting said second stage input to said second stage output to energize said second stage second store to its first state from said energy source through said first stage input-output connecting means when said first stage first store is in its first state, means jointly responsive to said counting signal and said second stage first store being in its second state for placing said second stage second store in its second state, and apparatus operative upon termination of said counting signal comprising means responsive to the first stage second store being in its first state and the state of said second stage second store for placing said second stage first store in a state opposite to the state of said second stage second store.

Claim 35

A binary counter comprising an energy source, a counting signal source, and first and second stages each comprising an input and an output, first and second stores operative in first and second opposite states, said second store being connected to said stage output, said first stage input being connected to said energy source, said first stage output being connected to said second stage input, means for simultaneously applying said counting signal to said first and second stages, said first stage further comprising means jointly responsive to said counting signal and said first store being in its first state for connecting said first stage input to said first stage output to energize said first stage second store to its first state, second means jointly responsive to said counting signal and said first stage first store being in its second state for placing said first stage second store in its second state, apparatus operative upon termination of said counting signal comprising third means responsive to the state of said first stage second store for placing said first stage first store in a state opposite to the state of the first stage second store, said second stage further comprising means jointly responsive to said counting signal and said second stage first store being in its first state for connecting said second stage input to said second stage output to energize said second stage second store to its first state from said energy source through said first stage input-output connecting means when said first stage first store is in its first state, means jointly responsive to said counting signal and said second stage first store being in its second state for placing said second stage second store in its second state, and apparatus operative upon termination of said counting signal comprising means responsive to the first stage second store being in its first state and the state of said second stage second store for placing said second stage first store in a state opposite to the state of said second stage second store.