Binary pulse rate multipliers

Claim 1

A binary pulse rate multiplier suitable for implementation in integrated circuit elements, the binary pulse rate multiplier including a progressive binary pulse counter comprising: a. n stages of flip-flops, each flip-flop being of a type which delays a change in its output stage until the initiating input to the flip-flop has terminated; b. a single input line for receiving pulses to be counted; c. a connection between the single input line and input to the flip-flop of the first stage; d. a multiple enabling means associated with and following each flip-flop stage and having a first input connected to the output of the associated flip-flop and a second input from the single input line; e. a cascaded chain of gating arrangements, the input to said chain comprising outputs from the first and second flip-flop stages, each gating arrangement of the chain subsequent to the first stage having connected as an additional input an output from respective flip-flop stages subsequent to the second stage; f. means for connecting as an additional input to the enabling means between the first and second flip-flop stages that output from the first flip-flop stage which serves as an input to said chain; g. means connecting outputs from said gating arrangements as additional inputs to respective enabling means subsequent to that following the second flip-flop stage; and wherein h. the enabling means following each flip-flop, except the flipflop of stage n, provides the input for the next successive flip-flop and each enabling means provides a pulse output which is connected without differentiation or pulse shaping to a combined output pulse line through n individual pulse rate selection gates so that energization of appropriate selection gates creates an output pulse trAin in the combined output pulse line having an average repetition rate which is equal to the average repetition rate of the input pulses applied to the counter on the single input pulse line multiplied by the sum of the binary fractions associated with the energized selection gates.