Character addressing in a word oriented computer system

Claim 2

In a word-oriented data processing system having an addressable main memory device having a plurality of addressable storage locations, character addressing apparatus comprising: word-oriented memory addressing control means for accessing ones of the addressable storage locations character-addressing means coupled to said word-oriented addressing control means for selecting a predetermined one of a plurality of character sizes from one of a plurality of character locations in the accessed ones of said addressable storage locations and having character justification means for transferring and positioning selected characters to a justified location adjacent the binary point in a work-oriented system during character reading operations, and sign extension control means for selectively extending the sign of the accessed character to fill all digit positions of a word in said word-oriented system other than used for said character; and character-addressing control means coupled to said characteraddressing means for selectively activating said characteraddressing means for accessing said predetermined one character size.

Claim 3

Character addressing apparatus as in claim 1 wherein said character-addressing means includes character positioning means for positioning selected characters from a predetermined justified location adjacent the binary point in a word-oriented system to one of a plurality of character locations in said word-oriented system during writing operations.

Claim 4

Character addressing apparatus as in claim 1 wherein said character-addressing means includes character accessing incrementing means for accessing predetermined sequences of predetermined size characters in said addressable main memory device.

Claim 5

Character addressing apparatus as in claim 3 wherein said character addressing incrementing means includes word off-set means for determining the absolute address, in conjunction with the programmed address, of the word in said main memory device; character offset means for determining the character location of the selected character within said word; word increment means for incrementing said word offset means in a predetermined; and character increment means for altering said character offset means in a predetermined amount for accessing characters in a predetermined sequence.

Claim 6

Character addressing control apparatus for use with an addressable memory having a plurality of independently addressable storage registers for storing data and instruction word manifestations and having an instruction storage register with at least a portion thereof adapted for storing a base relative memory address to be accessed in the memory section, an indicator for indicating character indexing will be performed, said character addressing control apparatus comprising: word offset means for receiving signals indicative of a word offset; means for receiving signal manifestations indicative of a programmed base relative address for accessing a storage register; means for storing at least two selectively alterable base relative address constants and a memory area divider pointer address constant; first means for combining one of said base relative constants and the received programmed base relative address; second means operable substantially simultaneously with said first means for combining said second base relative address constants and the received programmed base relative address; control means for causing said first means and second means to combine said word offset signals with the respective results; selection means responsively coupled to said means for storing for evaluating said base relative address pointer constant for selective one of said sums as an alternative absolute memory address to be accessed in the addressable memory; memory accessing means for accessing said memory at said absolute addresS; and character offset means for receiving signals indicative of the character location in the word accessed by said absolute address; and character addressing means coupled to said character offset means for selecting the addressed character.

Claim 7

Character addressing control apparatus for use with an addressable memory having a plurality of independently addressable storage registers for storing data and instruction word manifestations and having an instruction storage register with at least a portion thereof adapted for storing a base relative memory address to be accessed in the memory section, an indicator for indicating character indexing will be performed, said character addressing control apparatus comprising: word offset means for receiving signals indicative of a word offset; means for receiving signal manifestations indicative of a programmed base relative address for accessing a storage register; means for storing at least two selectively alterable base relative address constants and a memory area divider pointer address constant; first means for combining one of said base relative constants and the received programmed base relative address; second means operable substantially simultaneously with said first means for combining said second base relative address constants and the received programmed base relative address; control means for causing said first means and second means to combine said word offset signals with the respective results; selection means responsively coupled to said means for storing for evaluating said base relative address pointer constant for selective one of said sums as an alternative absolute memory address to be accessed in the addressable memory; memory accessing means for accessing said memory at said absolute addresS; and character offset means for receiving signals indicative of the character location in the word accessed by said absolute address; and character addressing means coupled to said character offset means for selecting the addressed character.

Claim 8

Character addressing control apparatus as in claim 5, and further including address incrementing means for incrementing the character addresses of sequences of characters to be accessed.

Claim 9

Character addressing control apparatus as in claim 6 wherein said address incrementing means includes word incrementing means coupled to said word offset means for incrementing said word offset signals by a predetermined amount, and character incrementing means coupled to said character offset means for incrementing said character offset signals by a predetermined amount.

Claim 10

Character addressing control apparatus as in claim 7 and further including character size control means coupled to said character addressing means for controlling the size of the character to be accessed.

Claim 11

Character addressing control apparatus as in claim 8 wherein said character addressing means includes character justification means for transferring and positioning selected characters to a predetermined justified position in a word-oriented system during reading of the addressed character.

Claim 12

Character addressing control apparatus as in claim 9, wherein said character addressing means further include sign extension control means for selectively extending the size of the accessed character to fill all digit positions of a word other than used for said character.

Claim 13

Character addressing control apparatus as in claim 7 wherein said character addressing means includes character size control means for providing signals indicative of the selected character size; character offset control means coupled to said character offset means for providing character offset control signals in response to said signals indicative of character location; a plurality of groups of character transfer gate means coupled to said character size control means and said character offset control means, each group of said plurality character transfer gate means for accessing a selected character, and each group of said character transfer gate means having input means coupled to receive predetermined digit combinations of the word accessed from said absolute address, each of said digit combinations comprising a predetermined character location, and output means for transferring the character signals selected to a predetermined justified position.

Claim 14

Character addressing control apparatus as in claim 11 and further including sign fill control means for selectively providing a signal fill control signal when sign fill is required; gate means coupled to said sign fill control means and responsively coupled to the sign signal in said character signals selected for sign filling all digit positions not utilized by said character signals.

Claim 15

Character addressing control apparatus as in claim 7 wherein said character addressing means includes write-character means for providing a character of a predetermined size to be stored in memory; character size control means for providing signals indicative of the selected character size; character off-set control means coupled to said character offset means for providing signals indicative of the character location within a word; a plurality of groups of character transfer gate means coupled to said character size control means and said character offset control means, each group of said character transfer gate means having input means coupled to receive predetermined digit combinations form said write-character means, and output means for transferring the character signals to a predetermined character offset position.

Claim 16

Character addressing control apparatus as in claim 8 wherein said address incrementing means includes word increment signal means for providing word increment signals indicative of a predetermined word increment to be utilIzed in altering said word offset signals; character increment signal means for providing character increment signals utilized to altering said character offset signals for providing an effective plus or minus one displacement of the next character address to be accessed; adder means for combining said word increment signals with said word offset signals and said character increment signals with said character offset signals for providing a new incremented character address.

Claim 17

Character addressing control apparatus as in claim 9 wherein said adder means includes signal transfer means for carrying an overflow signal that results when said combination of said word increment signals and said character offset signals passes through the maximum permissible value of character offset for a selected one of said character sizes, said signal transfer means coupled in said adder means for causing said overflow signal to be combined with said word increment signals and said word offset signals.

Claim 18

In a word-oriented computer system having an addressable main memory device having a plurality of independently addressable storage registers and control circuits for selectively performing word-oriented operations and character oriented operations, character addressing apparatus comprising: instruction register means with at least a first portion for storing base address signals a base relative memory address, a second portion for storing signals indicating one of a plurality of word address indexing registers, a third portion for storing signals indicating one of a plurality character addressing control registers, a fourth portion for storing increment control signals controlling incrementing of said address indexing registers and said character addressing control registers, and a fifth portion for storing operation code signals identifying the operation to be performed; base relative address means for storing signals indicative of at least first and second selectively alterable base address constants, a memory area divider constant and an operation control field including character mode selection; a plurality of index register means for storing signals indicative of word address index value; first and second adder means for forming first and second sums of said base relative memory address and said first and second base address constants; second and third adder means for forming third and fourth sums of said index value and said first and second sums; a plurality of character addressing control means, each having a first portion for storing character offset signals for locating a character within a word, a second portion for storing word offset signals for use in determining the absolute address of the word to be accessed, a third portion for storing character increment signals for use in modifying said character offset signals, a fourth portion for storing word increment signals for use in modifying said word offset signals, a fifth portion for storing sign extension control signals for controlling sign extension of accessed characters, a sixth portion for storing character size multiple control signals for selecting one of a plurality of base character sizes, a seventh portion for storing character mode control signals for selecting one of a plurality of multiples of said base character sizes, an eighth portion for storing indexing selection control signals for selecting indexing of said index register means and said character addressing control means; adder control means for causing said second and third adder means for forming fifth and sixth sums of said word offset signals and said fourth and fifth sums; fifth adder means for forming an intermediate sum of said base reltive address and said word address index value, if any; fifth address control means for causing said fifth adder means to a result sum of said intermediate sum and said word offset signals; absolute address selection means coupled to said memory area divider constant, said third, fourth, and fifth adder means for seleCting an absolute memory address to access a word in the main memory device; accessed word storage means for storing a word read from said main memory device; character selection means coupled to said accessed word storage means, and said first, fifth, sixth and seventh portions of said character addressing control means for selecting and justifying the addressed character; character storage means for storing a predetermined justified character to be stored in said main memory device; character position means coupled to said character storage means and said first, fifth, sixth and seventh portions of said character addressing control means for positioning said justified character for writing in the character address indicated.

Claim 19

In a word-oriented computer system having an addressable main memory device having a plurality of independently addressable storage registers and control circuits for selectively performing word-oriented operations and character oriented operations, character addressing apparatus comprising: instruction register means with at least a first portion for storing base address signals a base relative memory address, a second portion for storing signals indicating one of a plurality of word address indexing registers, a third portion for storing signals indicating one of a plurality character addressing control registers, a fourth portion for storing increment control signals controlling incrementing of said address indexing registers and said character addressing control registers, and a fifth portion for storing operation code signals identifying the operation to be performed; base relative address means for storing signals indicative of at least first and second selectively alterable base address constants, a memory area divider constant and an operation control field including character mode selection; a plurality of index register means for storing signals indicative of word address index value; first and second adder means for forming first and second sums of said base relative memory address and said first and second base address constants; second and third adder means for forming third and fourth sums of said index value and said first and second sums; a plurality of character addressing control means, each having a first portion for storing character offset signals for locating a character within a word, a second portion for storing word offset signals for use in determining the absolute address of the word to be accessed, a third portion for storing character increment signals for use in modifying said character offset signals, a fourth portion for storing word increment signals for use in modifying said word offset signals, a fifth portion for storing sign extension control signals for controlling sign extension of accessed characters, a sixth portion for storing character size multiple control signals for selecting one of a plurality of base character sizes, a seventh portion for storing character mode control signals for selecting one of a plurality of multiples of said base character sizes, an eighth portion for storing indexing selection control signals for selecting indexing of said index register means and said character addressing control means; adder control means for causing said second and third adder means for forming fifth and sixth sums of said word offset signals and said fourth and fifth sums; fifth adder means for forming an intermediate sum of said base reltive address and said word address index value, if any; fifth address control means for causing said fifth adder means to a result sum of said intermediate sum and said word offset signals; absolute address selection means coupled to said memory area divider constant, said third, fourth, and fifth adder means for seleCting an absolute memory address to access a word in the main memory device; accessed word storage means for storing a word read from said main memory device; character selection means coupled to said accessed word storage means, and said first, fifth, sixth and seventh portions of said character addressing control means for selecting and justifying the addressed character; character storage means for storing a predetermined justified character to be stored in said main memory device; character position means coupled to said character storage means and said first, fifth, sixth and seventh portions of said character addressing control means for positioning said justified character for writing in the character address indicated.

Claim 20

Character addressing apparatus as in claim 16 wherein said character selection means includes character size control means for providing signals indicative of the selected character size; character offset control means coupled to said character offset means for providing character offset control signals in response to said signals indicative of character location; a plurality of groups of character transfer gate means coupled to said character size control means and said character offset control means, each group of said plurality character transfer gate means for accessing a selected character, and each group of said character transfer gate means having input means coupled to receive predetermined digit combinations of the word accessed from said absolute address, each of said digit combinations comprising a predetermined character location, and output means for transferring the character signals selected to a predetermined justified position.

Claim 21

Character addressing apparatus as in claim 17 and further including sign fill control means for selectively providing a sign fill control signal when sign fill is required; gate means coupled to said sign fill control means and responsively coupled to the sign signal in said character signals selected for sign filling all digit positions not utilized by said character signals.

Claim 22

Character addressing apparatus as in claim 18 wherein said character positioning means includes a plurality of groups of character transfer gate means, each of said groups coupled to said character storage means and having output means for transferring said justified character to a predetermined character offset position for recording in said main memory device.

Claim 23

Character addressing apparatus as in claim 16 and further including character address incrementing means for incrementing the character address of sequences of characters to be accessed.

Claim 24

Character addressing apparatus as in claim 20 wherein said character addressing incrementing means includes character indexing control means responsive to said character mode selection, said operation code selection, said character addressing control register selection, said increment mode selection in said instruction and said increment selection in the selection one of said character addressing control registers, for selecting character address incrementation; adder means for forming the sum of said word increment signals and said word offset signals and the sum of said character increment signals and said character offset signals.