US3731283A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Digital computer incorporating base relative addressing of instructions
Assignee: Individual
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Filing: 1971-04-13
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Granted: 1973-05-01
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Expires: 1991-04-13
Abstract
Abstract A relative addressing scheme for a digital computer which allows programs of instructions to be stored in the computer memory at locations which may be addressed relative to predetermined base values rather than at absolute assigned addresses to facilitate program relocation within the memory. The program address register is divided into two segments, namely, a base register selection segment and a displacement segment. During instruction acquisition, the base register selection segment is decoded to read out the contents of a selected base register and these contents are added to the displacement segment of the program address register to define the address of the instruction to be acquired.
Inventors
- 👤 L Carlson
- 👤 E Hervig
- 👤 K Oehlers
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 18:03
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/32; G06F9/322; G06F9/324; G06F9/321
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
194 words
In a digital computer, the combInation comprising: a. a memory for storinG a program of instructions and operands at addressable locations therein; b. a plurality oF discrete base storage registers for storing in relative form addresses in said memory, program control register means for storing digital signals of a first significance for identifying one of said plurality of base storage registers and of a second significance for representing the relative address to be used in acquiring the next instruction; d. adder means having first and second inputs and an output; e. means responsive to said signals of first significance for uniquely selecting one of said plurality of base storage registers and applying the contents thereof to a first input of said adder means; f. means for applying said signalS of second significance to the second input of said adder means; and g. means connected to the output of said adder means for selecting the instruction stored at the particular memory location defined by the sum of said contents of said uniquely selected one of said base storage register and said signals of second significance as the next instruction to be executed by said computer.
Claim 2
Dependent Claim
194 words
In a digital computer, the combInation comprising: a. a memory for storinG a program of instructions and operands at addressable locations therein; b. a plurality oF discrete base storage registers for storing in relative form addresses in said memory, program control register means for storing digital signals of a first significance for identifying one of said plurality of base storage registers and of a second significance for representing the relative address to be used in acquiring the next instruction; d. adder means having first and second inputs and an output; e. means responsive to said signals of first significance for uniquely selecting one of said plurality of base storage registers and applying the contents thereof to a first input of said adder means; f. means for applying said signalS of second significance to the second input of said adder means; and g. means connected to the output of said adder means for selecting the instruction stored at the particular memory location defined by the sum of said contents of said uniquely selected one of said base storage register and said signals of second significance as the next instruction to be executed by said computer.
Claim 3
Dependent Claim
23 words
Apparatus as in claim 1 and further including means for incrementing said signals of second significance each time the next instruction is selected.
Claim 4
Dependent Claim
204 words
In a digital computer of the type having a memory for storing a program of instructions and operands at addressable locations therein, apparatus for generating the address of the next instruction to be selected from said memory, comprising: a. a plurality of discrete base storage registers for storing address modifying signals therein; b. a program control register having first and second sections for at least temporarily storing signals of first and second significance, said signals of first significance identifying a given one of said plurality of base storage registers, said signals of second significance representing the relative address of said next instruction; c. adder means; d. means responsive to the signals of first significance stored in said first section of said program control register for uniquely reading out the contents of one of said plurality of base storage registers to one input of said adder means; e. means for applying said signals of second significance to a second input of said adder means; and f. means responsive to the output of said adder means for accessing the particular instruction stored in said memory at the address represented by the sum of the signals applied to said first and second inputs of said adder means.
Claim 5
Dependent Claim
204 words
In a digital computer of the type having a memory for storing a program of instructions and operands at addressable locations therein, apparatus for generating the address of the next instruction to be selected from said memory, comprising: a. a plurality of discrete base storage registers for storing address modifying signals therein; b. a program control register having first and second sections for at least temporarily storing signals of first and second significance, said signals of first significance identifying a given one of said plurality of base storage registers, said signals of second significance representing the relative address of said next instruction; c. adder means; d. means responsive to the signals of first significance stored in said first section of said program control register for uniquely reading out the contents of one of said plurality of base storage registers to one input of said adder means; e. means for applying said signals of second significance to a second input of said adder means; and f. means responsive to the output of said adder means for accessing the particular instruction stored in said memory at the address represented by the sum of the signals applied to said first and second inputs of said adder means.
Claim 6
Dependent Claim
36 words
Apparatus as in claim 3 and further including means for incrementing the signals of second significance stored in said second section of said program control register each time a new instruction is selected from said memory.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-04-30 | 1976-10-30 | 1977-05-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-04-30 | 1980-10-30 | 1981-05-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-04-30 | 1984-10-30 | 1985-05-01 | $7700.00 | Window Closed / Lapsed |