Contact bounce eliminator circuit with low standby power

Claim 2

A circuit for producing a single output pulse in response to the closing of a mechanical switch comprising: a flip-flop circuit including two inputs; a source of potential selectively connectible to either one of said inputs; and cross-coupled field effect transistor means, responsive to said potential source and connected across said inputs, for discharging an input when said potential is switched from one input to another, said transistor means dissipating virtually no power when said circuit is in the quiescent state.

Claim 3

A circuit as in claim 1 wherein said potential source is positive and said transistors are of the N-channel type.

Claim 4

A circuit as in claim 2 wherein said flip-flop comprises cross-connected NOR gates.

Claim 5

A circuit as in claim 1 wherein said potential source is negative and said transistors are of the P-channel type.

Claim 6

A circuit as in claim 4 wherein said flip-flop comprises cross-connected NAND gates.

Claim 7

A circuit as in claim 1 further comprising: mechanical switching means having first and second contacts respectively connected to said two inputs and a third contact connected to said source of potential for supplying potential alternately to said first and second contacts.

Claim 8

A circuit as in claim 6 wherein said switching means is a break-before-make switch.

Claim 9

A contact bounce eliminator circuit which can be fabricated on a single semiconductor substrate and which draws virtually no power when said circuit is in the quiescent state comprising: a pair of logic gates operative as a flip-flop circuit, each said logic gate constructed from complementary metal oxide semiconductor field effect transistors; each said gate having an input; a source of potential selectively connectible to either one of said inputs; and a pair of field effect transistors of the same conductivity type connected in cross-coupled fashion across said inputs.

Claim 10

A contact bounce eliminator circuit which can be fabricated on a single semiconductor substrate and which draws virtually no power when said circuit is in the quiescent state comprising: a pair of logic gates operative as a flip-flop circuit, each said logic gate constructed from complementary metal oxide semiconductor field effect transistors; each said gate having an input; a source of potential selectively connectible to either one of said inputs; and a pair of field effect transistors of the same conductivity type connected in cross-coupled fashion across said inputs.

Claim 11

A circuit as in claim 8 wherein: each said logic gate is a NOR circuit; said source of voltage is positive; and the conductivity of said pair of field effect transistors is N type.

Claim 12

A circuit as in claim 8 wherein: each said logic gate is a NAND circuit; said source of voltage is negative; and the conductivity of said pair of field effect transistors is P type.

Claim 13

A circuit as in claim 8 wherein: each said logic gate is a NOR circuit; said source of voltage is negative; the conductivity of said pair of field effect transistors is P type; and further comprising: capacitance means connected at each said input for opposing changes in potential at said inputs when said potential source is unconnected to either of said inputs.

Claim 14

A circuit as in claim 8 whererein: each said logic gate is a NAND circuit; said source of voltage is positive; the conductivity of said pair of field effect resistors is N type; and further comprising: capacitance means connected at each said input for opposing changes in potential at said inputs when said potential source is unconnected to either of said inputs.

Claim 15

A contact bounce eliminator circuit comprising: circuit means including a pair of inputs and a pair of outputs for generating complementary signals on said outputs; potential means selectively connectible to either one of said inputs for reversing the signals on said outputs; and first and second field effect transistors, the gate electrode of said first transistor and the output electrode of said second transistor being connected to one of said input pair and the gate electrode of said second transistor and the output electrode of said first transistor being connected to the other of said input pair, the input electrodes of said first and second transistors being connected to a reference potential, whereby virtually no current flows between said potential means and said reference potential while said bounce eliminator circuit is in the quiescent state.

Claim 16

A contact bounce eliminator circuit comprising: circuit means including a pair of inputs and a pair of outputs for generating complementary signals on said outputs; potential means selectively connectible to either one of said inputs for reversing the signals on said outputs; and first and second field effect transistors, the gate electrode of said first transistor and the output electrode of said second transistor being connected to one of said input pair and the gate electrode of said second transistor and the output electrode of said first transistor being connected to the other of said input pair, the input electrodes of said first and second transistors being connected to a reference potential, whereby virtually no current flows between said potential means and said reference potential while said bounce eliminator circuit is in the quiescent state.