Single pulse switch circuit

Claim 1

A single pulse logical switching circuit comprising in combination: means for supplying a single predetermined electrical signal; means directly connected to said single predetermined electrical signal supplying means for producing a pair of data signals having substantially equal and oppositely configured waveforms in response to said single predetermined electrical signal; means connected to the outputs of said data signal producing means for timely loading, storing, and unloading of said pair of data signals in response to predetermined clock pulses, said means consisting of a first bistable multivibrator having a trio of inputs and a pair of outputs, with a pair of the inputs thereof directly connected to the aforesaid data signal producing means for response to the pair of data signals produced thereby, respectively, and with the remaining input thereof adapted for response to said predetermined clock pulses, and a second bistable multivibrator having a trio of inputs and a pair of outputs, with a pair of inputs thereof respectively directly connected to the pair of outputs of said first bistable multivibrator, and with the remaining input thereof adapted for response to said predetermined clock pulses; means connected to said data signal loading, storing, and unloading means for the timely supplying of said clock pulses directly thereto, said means consisting of a clock pulse generator directly connected to the remaining inputs of the aforesaid first and second bistable multivibrators; and means directly connected to the outputs of said first and second bistable multivibrators of said data signals loading; storing, and unloading means for simultaneously gating predetermined data signals that are simultaneously stored therein and unloaded therefrom in such manner as to produce in timely succession a pair of similarly configured pulses of one clock period duration at the output thereof.