Logic sensing circuit having switch contact anti-bounce feature

Claim 2

A logic sensing circuit responsive to the change in state of a switch, said circuit comprising: A. bistable means including two inputs adapted to respond to alternate state changes of said switch, said bistable means including two outputs; B. first gate means coupled to receive said two bistable means outputs; and C. means for delaying the response of said bistable means to a change in state of said switch so that said two outputs provide simultaneous similar signal levels enabling said first gate means to produce a pulse.

Claim 3

A circuit as defined in claim 1 further comprising circuit means coupled to said bistable means outputs for inhibiting the producing of said pulse when said circuit means receives a first signal.

Claim 4

A circuit as defined in claim 2 wherein said circuit means includes means for automatically producing a pulse without a change in state of said switch when said first signal received by said circuit means is disabled.

Claim 5

A circuit as defined in claim 1 further comprising first means, coupled to receive one of said bistable means outputs and said produced pulse, for indicating a first function in accordance with the state of said switch and second means, coupled to receive the other of said bistable means outputs and said produced pulse, for indicating a second function in accordance with the state of said switch.

Claim 6

A circuit as defined in claim 1 wherein said bistable means include two further gate means in circuit arrangement, at least one of said two further gate means including a node input bypassing the input gating elements of said gate means, and wherein said means for delaying includes capacitive means in circuit with said node input.

Claim 7

A circuit as defined in claim 5 wherein any contact bounce produced by the change in state of said switch does not affect operation of said circuit when said capacitive means is in a discharged condition.

Claim 8

A circuit as defined in claim 5 wherein each of said two further gate means includes a node input and wherein each of said node inputs includes a capacitive means in circuit with said node input, wherein in response to a change in state of said switch one of said capacitive means discharges and the other of said capacitive means charges, and wherein said first gate means produces a pulse while said other of said capacitive means charges to a predetermined threshold value.

Claim 9

A logic sensing circuit comprising: A. bistable means having two inputs and two outputs; B. means responsive to a change in state of said inputs for delaying a change in state of one of said outputs; and C. means responsive to said delayed change in state of one of said outputs for producing a pulse during said delay in response to said change in state of said inputs.

Claim 10

A logic sensing circuit comprising: A. bistable means having two inputs and two outputs; B. means responsive to a change in state of said inputs for delaying a change in state of one of said outputs; and C. means responsive to said delayed change in state of one of said outputs for producing a pulse during said delay in response to said change in state of said inputs.

Claim 11

A circuit as defined in claIm 8 wherein said bistable means includes first and second gate means in circuit arrangement, each of said gate means including a node input bypassing semiconductor gate elements in said gate means, and wherein said means for delaying includes first and second capacitors coupled to said node inputs of said first and second gate means respectively.

Claim 12

A logic sensing circuit comprising: A. a switch comprising an input coupled to a first potential and first and second outputs, said first potential coupled to one of said outputs depending on the state of said switch; B. bistable means comprising first and second gate means, each of said gate means including a node input bypassing gating elements included in said first and second gate means, said first and second gate means each having outputs and first and second inputs, said second input of each gate means coupled to said output of the other gate means, said first input of said first gate means coupled to said first output of said switch and said first input of said second gate means coupled to said second output of said switch; C. a first capacitor coupled between said node input of said first gate means and said first potential; D. a second capacitor coupled between said node input of said second gate means and said first potential; E. a second potential coupled to whichever one of said first inputs of said first and second gate means is not coupled to said first potential by said switch; and F. third gate means having first and second inputs coupled respectively to said outputs of said first and second gate means and having an output terminal at which a pulse is produced in response to a change in state of said switch.

Claim 13

A logic sensing circuit comprising: A. a switch comprising an input coupled to a first potential and first and second outputs, said first potential coupled to one of said outputs depending on the state of said switch; B. bistable means comprising first and second gate means, each of said gate means including a node input bypassing gating elements included in said first and second gate means, said first and second gate means each having outputs and first and second inputs, said second input of each gate means coupled to said output of the other gate means, said first input of said first gate means coupled to said first output of said switch and said first input of said second gate means coupled to said second output of said switch; C. a first capacitor coupled between said node input of said first gate means and said first potential; D. a second capacitor coupled between said node input of said second gate means and said first potential; E. a second potential coupled to whichever one of said first inputs of said first and second gate means is not coupled to said first potential by said switch; and F. third gate means having first and second inputs coupled respectively to said outputs of said first and second gate means and having an output terminal at which a pulse is produced in response to a change in state of said switch.

Claim 14

A logic sensing circuit responsive to the change in state of a switch, said circuit comprising: A. bistable means comprising two inputs adapted to respond to alternate state changes of said switch, said bistable means further comprising two outputs and two gate means in circuit arrangement between said two inputs and said two outputs, at least one of said two gate means including a node input bypassing the input gate elements of said gate means; and B. means for delaying the response of said bistable means to a change in state of said switch, said means for delaying including capacitive means in circuit with said node input.

Claim 15

A logic sensing circuit responsive to the change in state of a switch, said circuit comprising: A. bistable means comprising two inputs adapted to respond to alternate state changes of said switch, said bistable means further comprising two outputs and two gate means in circuit arrangement between said two inputs and said two outputs, at least one of said two gate means including a node input bypassing the input gate elements of said gate means; and B. means for delaying the response of said bistable means to a change in state of said switch, said means for delaying including capacitive means in circuit with said node input.

Claim 16

A circuit as defined in claim 11 further comprising means responsive to said delayed change in state of one of said outputs for producing a signal during said delay in response to a change in state of said switch.

Claim 17

A circuit as defined in claim 12 further comprising circuit means coupled to said bistable means outputs for inhibiting the producing of said signal when said circuit means receives a first signal.