Memory cell with reduced voltage supply while writing

Claim 5

A matrix of memory cells arranged in rows and columns wherein each memory cell comprises flip-flop circuit comprising a pair of cross-coupled inverter circuits each formed of a pair of transistors, and a transistor for enabling binary data to be read from, or stored within the flip-flop circuit and including a voltage supply means for lowering the voltage of a row of memory cells during a write operation to a voltage sufficiently high to maintain the said row of memory cells in the static mode, said row including a said memory cell into which a binary signal is to be stored, and wherein said binary signal to be stored is transmitted through said transistor to said memory cell.

Claim 6

A matrix of memory cells arranged in rows and columns wherein each memory cell comprises flip-flop circuit comprising a pair of cross-coupled inverter circuits each formed of a pair of transistors, and a transistor for enabling binary data to be read from, or stored within the flip-flop circuit and including a voltage supply means for lowering the voltage of a row of memory cells during a write operation to a voltage sufficiently high to maintain the said row of memory cells in the static mode, said row including a said memory cell into which a binary signal is to be stored, and wherein said binary signal to be stored is transmitted through said transistor to said memory cell.

Claim 7

A matrix of memory cells as in claim 3 wherein said pairs of transistors forming said inverter circuits comprise complimentary MOS transistors.

Claim 8

A matrix of memory cells as in claim 4 wherein said voltage supply means includes means for lowering the supply voltage to a value at least as great as the absolute value of the largest voltage threshold of the transistors comprisIng the flip-flop circuit.

Claim 9

A matrix of memory cells as in claim 5 wherein said voltage supply means comprises: a. a voltage source; b. a voltage divider circuit comprising at least first and second serially connected transistors, said first transistor being connected to said voltage source, and wherein the junction between said first and second transistors defines an output node; c. a third transistor connected between said second transistor and a reference voltage, said third transistor being normally-nonconductive; d. a fourth transistor, connected between said voltage source and said output supply voltage node, which is normally conducting so that the voltage at said output supply voltage node is normally the same as said voltage source; and e. means for turning off said fourth transistor and turning on said third transistor during a write operation so that current flows through said voltage divider and the voltage at said output node is determined by the relative impedances of the transistors forming the voltage divider circuit.

Claim 10

A matrix of memory cells as in claim 6 including means for automatically regulating the supply voltage to compensate for changes in the threshold values of said transistors in said row.

Claim 11

A matrix of memory cells as in claim 7 wherein said automatic regulating means comprises connecting the gate of said second complimentary MOS transistor to said output supply voltage node.

Claim 12

A circuit for lowering the supply voltage to one or a plurality of semiconductor memory cells during a write operation, comprising: a. a voltage source; b. a voltage divider circuit comprising at least first and second serially connected transistors, said first transistor being connected to said voltage source, and wherein the junction between said first and second transistors defines an output node; c. a third transistor connected between said second transistor and a reference voltage, said third transistor being normally-nonconductive; d. a fourth transistor, connected between said voltage source and said output supply voltage node, which is normally conducting so that the voltage at said output supply voltage node is normally the same as said voltage source; and e. means for turning off said fourth transistor and turning on said third transistor during a write operation so that current flows through said voltage divider and the voltage at said output node is determined by the relative impedances of the transistors forming the voltage divider circuit.

Claim 13

A circuit for lowering the supply voltage to one or a plurality of semiconductor memory cells during a write operation, comprising: a. a voltage source; b. a voltage divider circuit comprising at least first and second serially connected transistors, said first transistor being connected to said voltage source, and wherein the junction between said first and second transistors defines an output node; c. a third transistor connected between said second transistor and a reference voltage, said third transistor being normally-nonconductive; d. a fourth transistor, connected between said voltage source and said output supply voltage node, which is normally conducting so that the voltage at said output supply voltage node is normally the same as said voltage source; and e. means for turning off said fourth transistor and turning on said third transistor during a write operation so that current flows through said voltage divider and the voltage at said output node is determined by the relative impedances of the transistors forming the voltage divider circuit.

Claim 14

A circuit as in claim 9 wherein the third transistor is comparatively larger in size than said first and second transistors so that the voltage drop thereacross is small relative to that across said first and second transistors during a write operation.

Claim 15

A circuit as in claim 10 wherein the size of said second transistor is relatively large compared with said first transistor so that there is a greater voltage drop across said first transistor during a write operation.

Claim 16

A circuit as in claim 9 wherein each memory cell includes a flip-flop comprising four transistors and wherein said supply voltage lowering means includes means for lowering the supply voltage to a value at least as great as the absolute value of the largest voltage threshold of the transistors comprising said binary flip-flop.

Claim 17

A circuit as in claim 12 wherein said flip-flop transistors comprise pairs of complimentary MOS transistors.

Claim 18

A circuit as in claim 13 including means for automatically regulating the supply voltage during the reduced voltage period to compensate for changes in threshold values of the transistors forming said memory cells.

Claim 19

A circuit as in claim 14 wherein said automatic regulating means comprises connecting the gate of said second transistor of said supply voltage lowering circuit to said output supply voltage node thereof.

Claim 20

A circuit as in claim 9 wherein each memory cell includes a flip-flop comprising four tranSistors and wherein said supply voltage lowering means includes means for lowering the supply voltage to a value of approximately twice as great as the absolute value of the largest voltage threshold of the transistors comprising the binary flip-flop.

Claim 21

A circuit as in claim 16 wherein said flip-flop transistors comprise pairs of complimentary MOS transistors.

Claim 22

A circuit as in claim 17 including means for automatically regulating the voltage during the reduced voltage period to compensate for changes in threshold values of the transistors forming said memory cells.

Claim 23

A circuit as in claim 18 wherein said automatic regulating means comprises connecting the gate of said second transistor of said supply voltage lowering circuit to said output supply voltage node thereof.

Claim 24

In a static binary semiconductor memory cell operable in a read and write mode which comprises a. a binary flip-flop comprising i. first and second binary logic invertor circuits each having an input and an output and each connected between a supply voltage and a reference voltage; ii. first means for connecting the output of said first inverter circuit with the input of said second inverter circuit and defining a first node thereat, iii. second means for connecting the input of said first inverter circuit with the output of said second inverter circuit and defining a second node thereat, said second node defining the output of said binary flip-flop, and b. read/write switching means having an output connected to said first node, means for rendering the same conducting during a read operation to enable the binary state of said flip-flop to be determined at the input thereof, and means for rendering the same conducting during a write operation to enable binary signals provided at the input thereof to be sent to said flip-flop circuit to set the binary state thereof, and wherein the improvement comprises: means for lowering the supply voltage to said flip-flop circuit during a write operation to reduce the current therethrough while maintaining said memory cell in the static mode.

Claim 25

In a static binary semiconductor memory cell operable in a read and write mode which comprises a. a binary flip-flop comprising i. first and second binary logic invertor circuits each having an input and an output and each connected between a supply voltage and a reference voltage; ii. first means for connecting the output of said first inverter circuit with the input of said second inverter circuit and defining a first node thereat, iii. second means for connecting the input of said first inverter circuit with the output of said second inverter circuit and defining a second node thereat, said second node defining the output of said binary flip-flop, and b. read/write switching means having an output connected to said first node, means for rendering the same conducting during a read operation to enable the binary state of said flip-flop to be determined at the input thereof, and means for rendering the same conducting during a write operation to enable binary signals provided at the input thereof to be sent to said flip-flop circuit to set the binary state thereof, and wherein the improvement comprises: means for lowering the supply voltage to said flip-flop circuit during a write operation to reduce the current therethrough while maintaining said memory cell in the static mode.

Claim 26

A static binary semiconductor memory cell as in claim 20 wherein said first and second binary logic inverter circuits each comprise a pair of MOS transistors, and said read/write switching means also comprises an MOS transistor.

Claim 27

A static binary semiconductor memory cell as in claim 21 wherein said supply voltage lowering means includes means for lowering the supply voltage to a value at least as great as the absolute value of the largest voltage threshold of the transistors comprising the binary flip-flop.

Claim 28

A static binary semiconductor memory cell as in claim 22 wherein said pairs of MOS transistors comprise complimentary MOS transistors.

Claim 29

A static binary semiconductor memory cell as in claim 22 including means for automatically regulating the supply voltage during the reduced voltage period to compensate for changes in threshold values of said transistors forming the memory cell.

Claim 30

A static binary semiconductor memory cell as in claim 21 wherein said supply voltage lowering means includes means for lowering the supply voltage to a value of approximately twice as great as the absolute value of the largest voltage threshold of the transistors comprising the binary flip-flop.

Claim 31

A static binary semiconductor memory cell as in claim 25 wherein said pairs of MOS transistors comprise complimentary MOS transistors.

Claim 32

A static binary semiconductor memory cell as in claim 26 including means for automatically regulating the supply voltage during the reduced voltage period to compensate for changes in threshold values of said transistors forming the memory cell.

Claim 33

A static binary semiconductor memory cell as in claim 20 wherein said supply voltage lowering means comprises: a. a voltage source; b. a voltage divider circuit comprising at least first and second serially connected transistors, said first transistor Being connected to said voltage source, and wherein the junction between said first and second transistors defines an output node; c. a third transistor connected between said second transistor and a reference voltage, said third transistor being normally-nonconductive; d. a fourth transistor, connected between said voltage source and said output supply voltage node, which is normally conducting so that the voltage at said output supply voltage node is normally the same as said voltage source; and e. means for turning off said fourth transistor and turning on said third transistor during a write operation so that current flows through said voltage divider and the voltage at said output node is determined by the relative impedances of the transistors forming the voltage divider circuit.

Claim 34

A static binary semiconductor memory cell as in claim 28 wherein said supply voltage means includes means for lowering the supply voltage to a value at least as great as the absolute value of the largest voltage threshold of the transistors comprising the binary flip-flop.

Claim 35

A static binary semiconductor memory cell as in claim 29 wherein each of said binary logic inverter circuits comprises a pair of complimentary MOS transistors.

Claim 36

A static binary semiconductor memory cell as in claim 30 including means for automatically regulating the supply voltage during the reduced voltage period to compensate for changes in threshold values of said transistors forming the memory cell.

Claim 37

A static binary semiconductor memory cell as in claim 31 wherein said automatic regulating means comprises connecting the gate of said second transistor of said supply voltage lowering means to said output supply voltage node thereof.

Claim 38

A static binary semiconductor memory cell as in claim 28 wherein said supply voltage lowering means includes means for lowering the supply voltage to a value of approximately twice as great as the absolute value of the largest voltage threshold of the transistors comprising the binary flip-flop.

Claim 39

A static binary semiconductor memory cell as in claim 33 wherein each of said binary logic inverter circuits comprises a pair of complimentary MOS transistors.

Claim 40

A static binary semiconductor memory cell as in claim 34 including means for automatically regulating the supply voltage during the reduced voltage period to compensate for changes in threshold values of said transistors forming the memory cell.

Claim 41

A static binary semiconductor memory cell as in claim 35 wherein said automatic regulating means comprises connecting the gate of said second transistor of said supply voltage lowering means to said output supply voltage node thereof.