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US3656010A
Expired / Lapsed
US
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Transistorized master slave flip-flop circuit
Assignee: US Philips Corp
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Filing: 1969-12-09
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Granted: 1972-04-11
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Expires: 1989-12-09
Abstract
Abstract A master slave flip-flop having lower dissipation and for a reduced number of cross-overs by the use of inverse logic, with a correct choice of the length width ratios of the channels of the field-effect transistors in order to prevent untimely changes of state are prevented.
Inventors
- 👤 Bernardus Johannes Mari Huyben
- 👤 Evert Jan Van Barneveld
- 👤 Louwrens Marinus Van De Steen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 16:19
CPC Classifications
H; H04; H04N; H04N5/00; H04N5/44; H04N5/60; H04N5/62
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
378 words
A master-slave flip-flop, comprising a master flip-flop triggerable to two stable states; a slave flip-flop triggerable to two stable states; a first gate circuit means for triggering the master flip-flop to a state corresponding to the state of the slave flip-flop in response to a first voltage level of a clock signal and comprising a first transistor having a control input for receiving the clock signal and a main current path, a second transistor having a control input connected to a first output of the slave flip-flop and a main current path connected on one side to a first input of the master flip-flop and on the other side through the main current path of the first transistor to a source of constant potential, a third transistor having a control input connected to a second output of the slave flip-flop and a main current path connected on one side to a second input of the master flip-flop and on the other side through the main current path of the first transistor to the source of constant potential; and a second gate circuit means for triggering the slave flipflop into a state corresponding to the state of the master flipflop in response to a second voltage level of the clock signal and comprising a fourth transistor having a control input connected to the clock signal and a main current path connected on one side to the source of constant potential, a fifth transistor having a control input connected to a first output of the master flip-flop and a main current path connected in parallel with the main current path of the fourth transistor, first coupling means for connecting the main current paths of the fourth and fifth transistors to a first input of the slave flipflop, a sixth transistor having a control input connected to the clock signal and having a main current path connected to the source of constant potential, a seventh transistor having a control input connected to a second output of the master flipflop and having a main current path connected in parallel with the main current path of the sixth transistor, and second coupling means for connecting the main current paths of the sixth and seventh transistors to a second input of the slave flip-flop.
Claim 2
Dependent Claim
378 words
A master-slave flip-flop, comprising a master flip-flop triggerable to two stable states; a slave flip-flop triggerable to two stable states; a first gate circuit means for triggering the master flip-flop to a state corresponding to the state of the slave flip-flop in response to a first voltage level of a clock signal and comprising a first transistor having a control input for receiving the clock signal and a main current path, a second transistor having a control input connected to a first output of the slave flip-flop and a main current path connected on one side to a first input of the master flip-flop and on the other side through the main current path of the first transistor to a source of constant potential, a third transistor having a control input connected to a second output of the slave flip-flop and a main current path connected on one side to a second input of the master flip-flop and on the other side through the main current path of the first transistor to the source of constant potential; and a second gate circuit means for triggering the slave flipflop into a state corresponding to the state of the master flipflop in response to a second voltage level of the clock signal and comprising a fourth transistor having a control input connected to the clock signal and a main current path connected on one side to the source of constant potential, a fifth transistor having a control input connected to a first output of the master flip-flop and a main current path connected in parallel with the main current path of the fourth transistor, first coupling means for connecting the main current paths of the fourth and fifth transistors to a first input of the slave flipflop, a sixth transistor having a control input connected to the clock signal and having a main current path connected to the source of constant potential, a seventh transistor having a control input connected to a second output of the master flipflop and having a main current path connected in parallel with the main current path of the sixth transistor, and second coupling means for connecting the main current paths of the sixth and seventh transistors to a second input of the slave flip-flop.
Claim 3
Dependent Claim
150 words
A circuit as claimed in claim 1, wherein the master flip-flop comprises an eighth transistor having a control input connected to the main current path of the second transistor and having a main current path connected to the source of constant potential, and a ninth transistor cross coupled with the eighth transistor and having a control input connected to the main current path of the third transistor and having a main current path connected to the source of constant potential; and wherein the slave flip-flop comprises a tenth transistor having a control input connected to the control input of the second transistor and having a main current path connected to the first coupling means and an eleventh transistor cross coupled with the tenth transistor and having a control input connected to the control input of the third transistor and having a main current path connected to the second coupling means.
Claim 4
Dependent Claim
117 words
A circuit as claimed in claim 2, wherein the first transistor of the first gate circuit and the fourth and sixth transistors of the second gate circuits are isolated-gate field-effect transistors, further comprising a separate corresponding resistance element connecting the main current paTh of each of the isolated-gate field-effect transistors to a second source of constant potential, wherein the quotient of the length-width ratio of the channel of the first transistor divided by the resistance of the corresponding resistance element is larger than the quotient of the length-width ratio of the channel of either the fourth transistor and the resistance of the corresponding resistance element or the sixth transistor and the resistance of the corresponding resistance element.
Claim 5
Dependent Claim
112 words
A circuit as claimed in claim 1, further comprising two sets of isolated-gate field-effect transistors, each set comprising at least two isolated-gate field-effect transistors and each isolated-gate field-effect transistor having a shunt connected between the gate and drain terminals thereof, means for connecting the channels of each set of field-effect transistors in a separate series circuit, means for connecting the main current paths of the parallel connected fourth and fifth transistors to a second source of constant potential through one of the series circuits, and means for connecting the main current paths of the parallel connected sixth and seventh transistors to the second source of constant potential through the other series circuit.
Claim 6
Dependent Claim
76 words
A circuit as claimed in claim 1, wherein the main conduction path of the second transistor is connected to the control input thereof through the control input and the main conduction path of the fifth transistor and the first coupling means, and wherein the main conduction path of the third transistor is connected to the control input thereof through the control input and the main conduction path of the seventh transistor and the second coupling means.
Claim 7
Dependent Claim
21 words
A circuit as claimed in claim 1, wherein all the elements comprise isolated-gate field-effect transistors integrated on a single semi-conductor substrate.
Claim 8
Dependent Claim
98 words
A circuit as claimed in claim 1, wherein the slave flip-flop comprises two transistors, each transistor of the slave flip-flop having a control input and a main conduction path, wherein the current to the main conduction path of each transistor of the slave flip-flop varies as a function of the difference between signals applied to the control input and one end of the main conduction path of each slave flip-flop transistor, said one end of each transistor of the slave flip-flop is connected to a separate output of the second gate circuit means for triggering the slave flip-flop.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-04-11 | 1975-10-11 | 1976-04-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-04-11 | 1979-10-11 | 1980-04-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-04-11 | 1983-10-11 | 1984-04-11 | $7700.00 | Window Closed / Lapsed |