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US3798617A
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Permanent storage memory and means for addressing
Assignee: Arris Technology Inc
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Filing: 1972-05-08
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Granted: 1974-03-19
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Expires: 1992-05-08
Abstract
Abstract A permanent storage memory comprises a data storing section in which data is stored in a predetermined manner at a plurality of address stations defined by intersecting rows and columns. A plurality of data nodes are operatively associated respectively with the columns of the memory and means are provided for addressing a selected row thereby to develop a plurality of data signals at said data nodes corresponding respectively to the stored bits at the addressed row. A second addressing means is effective to provide a unique signal corresponding to the selected column and is effective to initiate the transfer of data signals to an output terminal from a predetermined one of the data nodes.
Inventors
- 👤 A Varadi
- 👤 R Rubinstein
- 👤 S Radoff
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 16:35
CPC Classifications
G; G11; G11C; G11C17/00; G11C17/08; G11C17/10; G11C17/12; G11C7/00; G11C7/10; G11C7/1015; G11C7/1018; G11C8/00; G11C8/04
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
165 words
A permanent storage memory comprising a data storing section in which a plurality of information bits are stored in a predetermined manner at a plurality of address stations defined by intersecting lines of first and second types, said data storing section having a plurality of data nodes respectively operatively associated with said lines of said first type, first addressing means effective to address a selected line of said second type of said data storing section and to develop a plurality of data signals at said data nodes corresponding respectively to the stored bits at said addressed line, an output terminal, and means effective to successively and periodically transfer a data signal from each of said data nodes to said output terminal, said transferring means comprising second addressing means effective to produce a unique signal corresponding to a selected line of said first type and effective to initiate the transfer of said data signals to said output terminal from a predetermined one of said data nodes.
Claim 2
Dependent Claim
165 words
A permanent storage memory comprising a data storing section in which a plurality of information bits are stored in a predetermined manner at a plurality of address stations defined by intersecting lines of first and second types, said data storing section having a plurality of data nodes respectively operatively associated with said lines of said first type, first addressing means effective to address a selected line of said second type of said data storing section and to develop a plurality of data signals at said data nodes corresponding respectively to the stored bits at said addressed line, an output terminal, and means effective to successively and periodically transfer a data signal from each of said data nodes to said output terminal, said transferring means comprising second addressing means effective to produce a unique signal corresponding to a selected line of said first type and effective to initiate the transfer of said data signals to said output terminal from a predetermined one of said data nodes.
Claim 3
Dependent Claim
57 words
The memory of claim 1, in which said data storing section comprises a supplemental line of one of said first and second types having data stored therein in a unique pattern, and comprising means operatively connected between said supplemental line and said transferring means and effective when said supplemental line is addressed to disable said transferring means.
Claim 4
Dependent Claim
86 words
The memory of claim 2, in which data is stored at said address stations in one of two discrete logic conditions, all of said address stations in said supplemental line being of one of said logic conditions, and comprising logic means operatively connected to said supplemental line and switching means operatively connected to said logic means and effective when actuated to unconditionally place said output node in a reference condition, said logic means being effective when said supplemental line is addressed to actuate said switching means.
Claim 5
Dependent Claim
72 words
In the memory of claim 1, in which said signal transferring means comprises gating means, means operatively connecting said data nodes to said gating means, and means effective to produce timed scanning signals and to operatively connect said scanning signals to said gating means, said gating means being effective to operatively transfer said data signals to said output terminal upon the operative time coincidence of a data signal and a scanning signal.
Claim 6
Dependent Claim
143 words
The memory of claim 4, in which said scanning signal producing means comprises a shift register having a plurality of interconnected stages corresponding in number to the number of said data nodes, a corresponding plurality of output nodes respectively operatively associated with said data nodes at which said scanning signals are derived, and means controlled by an enabling signal and effective to initially operatively connect said second addressing means to said output nodes and to charge one of said output nodes corresponding to the selected one of said lines of said first type to a first signal level and the other of said output nodes to a second signal level and to disconnect said shift register stages from said output nodes, thereby to initiate the transfer of said data signals from the data node operatively associated with said one of said output nodes.
Claim 7
Dependent Claim
136 words
The memory of claim 5 in which said addressing means associated with said supplemental line comprises a plurality of logic gates each having a logic node and each receiving a different group of input address signals, said signals being effective to render one of said gates uniquely non-conductive, said connecting means comprising switch means actuated by said enabling signal and effective when so actuated to operatively respectively connect said logic node to said output nodes, means to precharge said output nodes to a first level during a first period, and means to discharge all but one of said output nodes through said logic gates other than said non-conductive one to a second level during a second period and to maintain that one of said output nodes operatively connected to said non-conductive gate at said first level.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-03-18 | 1977-09-17 | 1978-03-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-03-18 | 1981-09-17 | 1982-03-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-03-18 | 1985-09-17 | 1986-03-19 | $7700.00 | Window Closed / Lapsed |