Ternary memory cell

Claim 2

In combination, a regenerative circuit having first and second states comprising, a first complementary transistor pair, a second complementary transistor pair, means including direct current paths for interconnecting said first transistor pair with said second transistor pair such that said first and second transistor pairs are conductive in said first and second states respectively and such that each of said pairs is normally switched conductive when the other of said pairs is switched nonconductive, and circuit means for providing said regenerative circuit with a third, stable state in which both of said first and second transistor pairs are latched nonconductive, said circuit means including means for clamping said first and second transistor pairs nonconductive and latching means normally operative in response to concurrent nonconduction of said first and second transistor pairs for maintaining said clamping means operated.

Claim 3

In combination, a regenerative circuit having first and second states comprising, a first complementary transistor pair, a second complementary transistor pair, means including direct current paths for interconnecting said first transistor pair with said second transistor pair such that said first and second transistor pairs are conductive in said first and second states respectively and such that each of said pairs is normally switched conductive when the other of said pairs is switched nonconductive, circuit means for providing said regenerative circuit with a third, stable state in which both of said first and second transistor pairs are latched nonconductive, said circuit means including means for clamping said first and second transistor pairs nonconductive and latching means normally operative in response to concurrent nonconduction of said first and second transistor pairs for maintaining said clamping means operated, and triggering means for switching said regenerative circuit to said first and to said second states in responsive to first and second triggering signals respectively, and means responsive to said first triggering signal and to said second triggering signal for inhibiting operation of said latching means.

Claim 4

In combination, a regenerative circuit having first and second states comprising, a first complementary transistor pair, a second complementary transistor pair, means including direct current paths for interconnecting said first transistor pair with said second transistor pair such that said first and second transistor pairs are conductive in said first and second states respectively and such that each of said pairs is normally switched conductive when the other of said pairs is switched nonconductive, circuit means for providing said regenerative circuit with a third, stable state in which both of said first and second transistor pairs are latched nonconductive, said circuit means including means for clamping said first and second transistor pairs nonconductive and latching means normally operative in response to concurrent nonconduction of said first and second transistor pairs for maintaining said clamping means operated, and triggering means for switching said regenerative circuit to said first and to said second states in responsive to first and second triggering signals respectively, and means responsive to said first triggering signal and to said second triggering signal for inhibiting operation of said latching means.

Claim 5

The combination of claim 2 further comprising an output terminal connected to a transistor of one of said transistor pairs, and means operative when said regenerative circuit is in said third state for connecting said output terminal to a predeterMined potential via a low impedance path.

Claim 6

In combination, a regenerative circuit having first and second states comprising, a first complementary transistor pair, a second complementary transistor pair, means including direct current paths for interconnecting said first transistor pair with said second transistor pair such that said first and second transistor pairs are conductive in said first and second states respectively and such that each of said pairs is normally switched conductive when the other of said pairs is switched nonconductive, circuit means for providing said regenerative circuit with a third, stable state in which both of said first and second transistor pairs are latched nonconductive, said circuit means including means for clamping said first and second transistor pairs nonconductive and latching means normally operative in response to concurrent nonconduction of said first and second transistor pairs for maintaining said clamping means operated, and triggering means for switching said regenerative circuit to said first and to said second states in response to first and second triggering signals respectively, and means responsive exclusively to nonconcurrent ones of said first and second triggering signals for inhibiting operation of said latching means.

Claim 7

In combination, a regenerative circuit having first and second states comprising, a first complementary transistor pair, a second complementary transistor pair, means including direct current paths for interconnecting said first transistor pair with said second transistor pair such that said first and second transistor pairs are conductive in said first and second states respectively and such that each of said pairs is normally switched conductive when the other of said pairs is switched nonconductive, circuit means for providing said regenerative circuit with a third, stable state in which both of said first and second transistor pairs are latched nonconductive, said circuit means including means for clamping said first and second transistor pairs nonconductive and latching means normally operative in response to concurrent nonconduction of said first and second transistor pairs for maintaining said clamping means operated, and triggering means for switching said regenerative circuit to said first and to said second states in response to first and second triggering signals respectively, and means responsive exclusively to nonconcurrent ones of said first and second triggering signals for inhibiting operation of said latching means.

Claim 8

A complementary cell having first and second states comprising, a first complementary transistor pair, a second complementary transistor pair, means including direct current paths for interconnecting said first transistor pair with said second transistor pair such that said first and second transistor pairs are conductive in said first and second states respectively, and such that each of said pairs is normally switched conductive after the other of said pairs is switched nonconductive, and means responsive to a predetermined triggering signal for switching a conductive one of said first and second transistor pairs nonconductive, the improvement comprising; means normally operative in response to concurrent nonconduction of said first and second transistor pairs for latching said first and second transistor pairs to maintain them nonconductive upon termination of said predetermined signal, whereby said cell is provided with a third, stable state.

Claim 9

A complementary cell having first and second states comprising, a first complementary transistor pair, a second complementary transistor pair, means including direct current paths for interconnecting said first transistor pair with said second transistor pair such that said first and second transistor pairs are conductive in said first and second states respectively, and such that each of said pairs is normally switched conductive after the other of said pairs is switched nonconductive, and means responsive to a predetermined triggering signal for switching a conductive one of said first and second transistor pairs nonconductive, the improvement comprising; means normally operative in response to concurrent nonconduction of said first and second transistor pairs for latching said first and second transistor pairs to maintain them nonconductive upon termination of said predetermined signal, whereby said cell is provided with a third, stable state.

Claim 10

A complementary cell having first and second states comprising, a first complementary transistor pair, a second complementary transistor pair, means including direct current paths for interconnecting said first transistor pair with said second transistor pair such that said first and second transistor pairs are conductive in said first and second states respectively, and such that each of said pairs is normally switched conductive after the other of said pairs is switched nonconductive, means responsive to a predetermined triggering signal for switching a conductive one of said first and second transistor pairs nonconductive, means normally operative in response to concurrent nonconduction of said first and second transistor pairs for latching said first and second transistor pairs to maintain them nonconductive upon termination of said predetermined signal, triggering means for switching said cell to said first and to said second states in response to first and second triggering signals respectively, and means responsive to said first triggering signal and to said second triggering signal for inhibiting operation of said latching means.

Claim 11

A complementary cell having first and second states comprising, a first complementary transistor pair, a second complementary transistor pair, means including direct current paths for interconnecting said first transistor pair with said second transistor pair such that said first and second transistor pairs are conductive in said first and second states respectively, and such that each of said pairs is normally switched conductive after the other of said pairs is switched nonconductive, means responsive to a predetermined triggering signal for switching a conductive one of said first and second transistor pairs nonconductive, means normally operative in response to concurrent nonconduction of said first and second transistor pairs for latching said first and second transistor pairs to maintain them nonconductive upon termination of said predetermined signal, triggering means for switching said cell to said first and to said second states in response to first and second triggering signals respectively, and means responsive to said first triggering signal and to said second triggering signal for inhibiting operation of said latching means.

Claim 12

A ternary cell comprising first and third transistors of a first conductivity type and second and fourth transistors of a second conductivity type, first and second output buses, means for connecting the collectors of said first and fourth transistors to said first bus and their bases to said second bus, means for connecting the collectors of said second and third transistors to said second bus and their bases to said first bus, clamping means operative for maintaining all of said transistors concurrently nonconductive, and latching means operative in response to concuRrent nonconduction in all of said transistors for operating said clamping means.

Claim 13

A ternary cell comprising first and third transistors of a first conductivity type and second and fourth transistors of a second conductivity type, first and second output buses, means for connecting the collectors of said first and fourth transistors to said first bus and their bases to said second bus, means for connecting the collectors of said second and third transistors to said second bus and their bases to said first bus, clamping means operative for maintaining all of said transistors concurrently nonconductive, and latching means operative in response to concuRrent nonconduction in all of said transistors for operating said clamping means.

Claim 14

A ternary cell in accordance with claim 7 further comprising, means for coupling the emitters of said first and third transistors to a first potential, and means for coupling the emitters of said second and fourth transistors to a second potential and wherein said latching means comprises means normally operative for operating said clamping means when the potentials on said first and second buses are both substantially equal to a third potential halfway between said first and second potentials.

Claim 15

A ternary cell in accordance with claim 8 wherein said clamping means includes first and second clamping circuits respectively operative for maintaining said first and second and said third and fourth transistors nonconductive, wherein each of said clamping circuits is operative in response to a signal at said third potential, and wherein said latching means includes a diode bus and first, second, third and fourth diodes, the anodes of all of said diodes being connected to said diode bus, the cathodes of said first and fourth diodes being connected to said clamping circuits, and the cathodes of said second and third diodes being connected to said first and second output buses, respectively.

Claim 16

A ternary cell in accordance with claim 7 wherein said clamping means includes first and second clamping circuits respectively operative for maintaining said first and second and said third and fourth transistors nonconductive; said cell further comprising means for operating said first and second clamping circuits in response to first and second triggering signals, respectively, and means for concurrently operating said first and second clamping circuits in response to a third triggering signal.

Claim 17

A ternary cell in accordance with claim 10 further comprising means for inhibiting operation of said latching means in response to said first triggering signal and to said second triggering signal.