Low power ring counter

Claim 2

A ring counter comprising master and slave sections having a plurality of stages, each said stage being connected between power and ground lines and including a pair of multiple input AND gates and a NOR gate connected to the outputs of said AND gates, means directly connecting the output of each said NOR gate to one AND gate of each of the other stages in both the master and slave sections, a first clock means connected to one AND gate of each stage in the master section, and a second alternating clock means connected to the one AND gate of each stage in the slave section and means for providing a set signal to put one stage in a state to initially provide a current path, whereby subsequent clock pulses cause the current path to shift from one stage to the next in the master and slave sections.

Claim 3

The ring counter of claim 1 wherein each said stage comprises a load transistor connected to a pair of leads each containing a plurality of logic transistors connected in series to said ground line, the gates of said logic transistors being connected to the load transistors of the other stages, and one of said leads containing an additional transistor whose gate is connected to one of said clock means.

Claim 4

The ring counter of claim 2 including means interconnecting certain of said logic transistors in said stages so that their gating function is shared between two stages.

Claim 5

The ring counter of claim 2 wherein said transistors are insulated gate field effect devices formed on a single integrated circuit semiconductor device.

Claim 6

The ring counter of claim 1 wherein said NOR gates of each stage in said master and slave sections each comprise a load transistor and said and gates comprise a first logic transistor in series with said load transistor, said logic transistors in a first and second pair of stages and a third and fourth pair of stages in both master and slave sections being connected through a first junction to said ground line through a pair of second logic transistors in series, a third pair of logic transistor each connected in series with a said load transistor of said first and fourth stages and to a second junction, and a fourth pair of logic transistors, each connected in series to a load transistor of said second and third stages and to a third junction, a fourth pair of logic transistors connected in series between said second junction and a fourth junction and a fifth pair of logic transistors connected in series between said third junction and said fourth junction, said logic transistors having gates connected directly to the outputs of said master and slave sections, a timing transistor connected to said fourth junction, and periodic clocking means connected to the gate of said timing transistor.