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US3139540A Expired / Lapsed US ⏱️ 0.0 years remaining

Asynchronous binary counter register stage with flip-flop and gate utilizing plurality of interconnected nor circuits

Assignee: Unisys Corp
•
Filing: 1962-09-27
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Granted: 1964-06-30
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Expires: 1982-09-27
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Abstract

No abstract record available.

Inventors

  • 👤 George T Osborne

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-25 03:25
CPC Classifications
H; H03; H03K; H03K23/00; H03K23/58; H03K21/00; H03K23/002; H03K3/00; H03K3/02; H03K3/027; H03K3/037

Claims Analysis

Total Claims: 2
Claim 1
Independent Claim 130 words
FOR USE IN A BINARY REGISTER, IN COMBINATION: (A) A FIRST PAIR OF TWO-STATE NOR CIRCUITS CROSS-COUPLED TO FORM A BISTABLE FLIP-FLOP IN WHICH THE NOR CIRCUITS ARE IN OPPOSITE STATES; (B) A SECOND PAIR OF CROSS-COUPLED TWO-STATE NOR CIRCUITS; (C) A THIRD PAIR OF TWO-STATE NOR CIRCUITS, EACH CROSSCOUPLED WITH RESPECTIVELY DIFFERENT NOR CIRCUITS OF THE SECOND PAIR; (D) MEANS COUPLING THE OUTPUT OF EACH OF THE NOR CIRCUITS OF THE FIRST PAIR TO THE INPUT OF RESPECTIVELY DIFFERENT NOR CIRCUITS OF THE THIRD PAIR; (E) MEANS COUPLING THE OUTPUT OF EACH OF THE NOR CIRCUITS OF THE SECOND PAIR TO THE INPUT OF RESPECTIVELY DIFFERENT NOR CIRCUITS OF THE FIRST PAIR; (F) AND AN INPUT TERMINAL CONNECTED TO THE INPUT OF EACH NOR CIRCUIT OF SAID SECOND PAIR.
Claim 2
Dependent Claim 130 words
FOR USE IN A BINARY REGISTER, IN COMBINATION: (A) A FIRST PAIR OF TWO-STATE NOR CIRCUITS CROSS-COUPLED TO FORM A BISTABLE FLIP-FLOP IN WHICH THE NOR CIRCUITS ARE IN OPPOSITE STATES; (B) A SECOND PAIR OF CROSS-COUPLED TWO-STATE NOR CIRCUITS; (C) A THIRD PAIR OF TWO-STATE NOR CIRCUITS, EACH CROSSCOUPLED WITH RESPECTIVELY DIFFERENT NOR CIRCUITS OF THE SECOND PAIR; (D) MEANS COUPLING THE OUTPUT OF EACH OF THE NOR CIRCUITS OF THE FIRST PAIR TO THE INPUT OF RESPECTIVELY DIFFERENT NOR CIRCUITS OF THE THIRD PAIR; (E) MEANS COUPLING THE OUTPUT OF EACH OF THE NOR CIRCUITS OF THE SECOND PAIR TO THE INPUT OF RESPECTIVELY DIFFERENT NOR CIRCUITS OF THE FIRST PAIR; (F) AND AN INPUT TERMINAL CONNECTED TO THE INPUT OF EACH NOR CIRCUIT OF SAID SECOND PAIR.

References Cited (Backward Citations)

No citation records indexed.

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1967-06-30 1967-12-30 1968-06-30 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1971-06-30 1971-12-30 1972-06-30 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1975-06-30 1975-12-30 1976-06-30 $7700.00 Window Closed / Lapsed

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