US3575610A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Scanning pulse generator
Assignee: NEC Corp
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Filing: 1968-09-09
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Granted: 1971-04-20
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Expires: 1988-09-09
Abstract
Abstract A device is described for generating a successive train of pulses on separate lines from a plurality of cascade-connected pulse generator stages. Each stage is composed of a pulse width expansion circuit driving a scanning pulse output circuit. A pair of square waves, one being the inversion of the other, is applied to each stage with one square wave being applied to the pulse width expansion circuit and the other to the scanning pulse output circuit. Each odd-numbered stage has its pulse width expansion circuit coupled to one square wave and its scanning pulse output circuit coupled to the other square wave. Each evennumbered stage has its circuit reversely connected to the square waves from the odd-numbered stages. Field effect transistors are employed to accomplish the pulse generation, thereby eliminating components such as resistors, capacitors and the like.
Inventors
- 👤 Toshio Okubo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 12:35
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/15; H03K5/15013; H03K5/1506; H03K5/15093; G; G11; G11C; G11C19/00; G11C19/18; G11C19/182; G11C19/184
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
313 words
A scanning pulse generator comprising: a plurality of paired inverter stages connected in cascade, each of said stages having an input and an output inverter circuit, each of said input and output inverter circuits comprising first and second field effect transistors, the drain electrode of said first transistor being connected directly to the source electrode of said second transistor to form serial connection of said first and second transistors, the gate anD source electrodes of said first transistor being coupled to one another to make said first transistor serve as a load for said second transistor, the drainsource common junction of said input inverter circuit being connected to the gate electrode of said second transistor of said output inverter circuit, the drain-source common junction of said output inverter circuit being connected to the gate electrode of said second transistor of said input inverter circuit of the immediately succeeding one of said stages, means for supplying a pulse of a first polarity to said gate-source common junction of said first transistor of said input inverter circuit of the oddnumbered ones of said stages, and to said gate-source common junction of said first transistor of said output inverter circuit of the even-numbered ones of said stages; means for supplying a pulse of a second polarity opposite to said first polarity to said gate-source common junction of said first transistor of said output inverter of the odd-numbered ones of said stages, and to said gate-source common junction of said first transistor of said input inverter circuit of the even-numbered ones of said stages; means for supplying a start pulse to the gate electrode of said second transistor of said input inverter circuit of the first of said stages, and means coupled to the drain-source common junction of said first and second transistors of said output inverter of each of said stages for deriving said scanning pulse.
Claim 2
Dependent Claim
313 words
A scanning pulse generator comprising: a plurality of paired inverter stages connected in cascade, each of said stages having an input and an output inverter circuit, each of said input and output inverter circuits comprising first and second field effect transistors, the drain electrode of said first transistor being connected directly to the source electrode of said second transistor to form serial connection of said first and second transistors, the gate anD source electrodes of said first transistor being coupled to one another to make said first transistor serve as a load for said second transistor, the drainsource common junction of said input inverter circuit being connected to the gate electrode of said second transistor of said output inverter circuit, the drain-source common junction of said output inverter circuit being connected to the gate electrode of said second transistor of said input inverter circuit of the immediately succeeding one of said stages, means for supplying a pulse of a first polarity to said gate-source common junction of said first transistor of said input inverter circuit of the oddnumbered ones of said stages, and to said gate-source common junction of said first transistor of said output inverter circuit of the even-numbered ones of said stages; means for supplying a pulse of a second polarity opposite to said first polarity to said gate-source common junction of said first transistor of said output inverter of the odd-numbered ones of said stages, and to said gate-source common junction of said first transistor of said input inverter circuit of the even-numbered ones of said stages; means for supplying a start pulse to the gate electrode of said second transistor of said input inverter circuit of the first of said stages, and means coupled to the drain-source common junction of said first and second transistors of said output inverter of each of said stages for deriving said scanning pulse.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-04-19 | 1974-10-19 | 1975-04-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-04-19 | 1978-10-19 | 1979-04-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-04-19 | 1982-10-19 | 1983-04-20 | $7700.00 | Window Closed / Lapsed |