Patent US3781689A successfully refreshed from Google Patents.
US3781689A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Tristate pulse generator for producing consecutive pair of pulses
Assignee: HP Inc
•
Filing: 1972-04-17
•
Granted: 1973-12-25
•
Expires: 1992-04-17
Abstract
Abstract An improved manually-triggerable pulse generator has a highimpedance output in one operating state and alternate high-andlow-level logic states of low output impedance in remaining operating states for operation as a source of test pulses in digital circuitry.
Inventors
- 👤 H Marshall
- 👤 R Adler
- 👤 G Gordon
- 👤 J Pipkin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 21:28
CPC Classifications
H; H03; H03L; H03L5/00; H03K; H03K17/00; H03K17/51; H03K17/56; H03K17/60; H03K17/66; H03K17/665; H03K17/666; H03K3/00; H03K3/02; H03K3/353; H03D; H03D7/00; H03D7/12; H03D7/125
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
134 words
A logic pulse source comprising: a pair of output signal stages connected to a common output, the signal stages being operable in non-conductive and conductive signal conditions for conducting signal current with respect to said common output in opposite conduction directions during operation in the respective conductive signal conditions; circuit means connected to apply to said output signal stages a sequence of an initial and a subsequent timing pulse in response to a trigger signal applied to said circuit means, the trailing edge of the initial timing pulse and the leading edge of the subsequent timing pulse being substantially coincident for sequentially operating each of said output signal stages in the respective conductive signal condition; and actuating means for selectively applying trigger signals to said circuit means for producing said sequence of timing pulses.
Claim 2
Dependent Claim
134 words
A logic pulse source comprising: a pair of output signal stages connected to a common output, the signal stages being operable in non-conductive and conductive signal conditions for conducting signal current with respect to said common output in opposite conduction directions during operation in the respective conductive signal conditions; circuit means connected to apply to said output signal stages a sequence of an initial and a subsequent timing pulse in response to a trigger signal applied to said circuit means, the trailing edge of the initial timing pulse and the leading edge of the subsequent timing pulse being substantially coincident for sequentially operating each of said output signal stages in the respective conductive signal condition; and actuating means for selectively applying trigger signals to said circuit means for producing said sequence of timing pulses.
Claim 3
Dependent Claim
243 words
A logic pulse source comprising: a pair of output signal stages connected to a common output, the signal stages being operable in non-conductive and conductive signal conditions for conducting signal current with respect to said common output in opposite conduction directions during operation in the respective conductive signal conditions; circuit means having an input and including: pair of amplifier circuits each of which operates on signals applied thereto above a selected threshold level; first differentiator means connected to said input and to one of said amplifier circuits, and second differentiator means connected to apply output signal from said one amplifier circuit to the other of said amplifier circuits for producing at the output of the second amplifier circuit a timing pulse having a leading edge substantially coincident with the trailing edge of the output signal from the first amplifier circuit; means coupled to the output of the first one of said amplifier circuits for producing another timing pulse having a leading edge substantially coincident with the leading edge of the output signal from the first amplifier circuit; said circuit means being connected to apply the timing pulses to said output signal stages in response to a trigger signal applied to the input of said circuit means for sequentially operating each of said output signal stages in the respective conductive signal condition; and actuating means for selectively applying trigger signals to the input of said circuit means for producing said sequence of timing pulses.
Claim 4
Dependent Claim
243 words
A logic pulse source comprising: a pair of output signal stages connected to a common output, the signal stages being operable in non-conductive and conductive signal conditions for conducting signal current with respect to said common output in opposite conduction directions during operation in the respective conductive signal conditions; circuit means having an input and including: pair of amplifier circuits each of which operates on signals applied thereto above a selected threshold level; first differentiator means connected to said input and to one of said amplifier circuits, and second differentiator means connected to apply output signal from said one amplifier circuit to the other of said amplifier circuits for producing at the output of the second amplifier circuit a timing pulse having a leading edge substantially coincident with the trailing edge of the output signal from the first amplifier circuit; means coupled to the output of the first one of said amplifier circuits for producing another timing pulse having a leading edge substantially coincident with the leading edge of the output signal from the first amplifier circuit; said circuit means being connected to apply the timing pulses to said output signal stages in response to a trigger signal applied to the input of said circuit means for sequentially operating each of said output signal stages in the respective conductive signal condition; and actuating means for selectively applying trigger signals to the input of said circuit means for producing said sequence of timing pulses.
References Cited (Backward Citations)
US3194979A
Cited
US3359433A
Cited
US3381088A
Cited
US3585407A
Cited
US3493842A
Cited
US3599098A
Cited
US3649851A
Cited
US3624518A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-12-24 | 1977-06-25 | 1977-12-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-12-24 | 1981-06-25 | 1981-12-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-12-24 | 1985-06-25 | 1985-12-25 | $7700.00 | Window Closed / Lapsed |