Microprogrammed terminal

Claim 2

A computer display terminal comprising: a. a source bus; b. a destination bus, said source bus and said destination bus defining a single data bus; c. a control keyboard operatively connected to said data bus for generating instruction signals; d. a display oriented single-bus processor operatively connected to said data bus for processing said instruction signals; e. a micro-instruction decoder operatively connected to said single-bus processor; f. a microprogrammed read-only memory operatively connected to said micro-instruction decoder and said data bus; g. a display operatively connected to said data bus; h. said single-bus processor accepting data from said data bus, modifying said data in accordance with a computationally complete instruction set specified by said micro-instruction decoder and microprogrammed read-only memory, and returning the processed data to said data bus; i. said processed data being applied from said data bus to said display for presentation of said instruction signals.

Claim 3

The terminal as claimed in claim 1 wherein said micro-instruction decoder includes logic circuit means operatively connected to said microprogrammed read-only memory for converting and decoding the data stored in said read-only memory into signals required by said single-bus processor in order to enable said processor to execute the selected instruction.

Claim 4

A microprogrammed display terminal comprising: a. a source bus; b. a destination bus, said source bus and said destination bus defining a single data bus; c. means operatively connected to said data bus for generating an instruction code; d. a processor bus operator operatively connected to said data bus for processing said instruction code; e. a micro-instructioN decoder operatively connected to said processor bus operator; f. a microprogrammed read-only memory operatively connected to said micro-instruction decoder and said data bus; and g. display means operatively connected to said data bus for presenting said instruction code; h. said instruction code being applied to said data bus; i. said processor bus operator accepting data from said data bus, modifying said accepted data in accordance with a computationally complete instruction set as specified by said micro-instruction decoder and microprogrammed read-only memory, and returning the processed data to said data bus; j. said processed data being applied to said display means for presentation via said data bus.

Claim 5

A microprogrammed display terminal comprising: a. a source bus; b. a destination bus, said source bus and said destination bus defining a single data bus; c. means operatively connected to said data bus for generating an instruction code; d. a processor bus operator operatively connected to said data bus for processing said instruction code; e. a micro-instructioN decoder operatively connected to said processor bus operator; f. a microprogrammed read-only memory operatively connected to said micro-instruction decoder and said data bus; and g. display means operatively connected to said data bus for presenting said instruction code; h. said instruction code being applied to said data bus; i. said processor bus operator accepting data from said data bus, modifying said accepted data in accordance with a computationally complete instruction set as specified by said micro-instruction decoder and microprogrammed read-only memory, and returning the processed data to said data bus; j. said processed data being applied to said display means for presentation via said data bus.

Claim 6

The terminal as claimed in claim 3 wherein said microprogrammed read-only memory includes means for storing hard wired programs.

Claim 7

The terminal as claimed in claim 3 wherein said micro-instruction decoder includes logic means to convert and decode the data stored in said read-only memory into signals required by said processor bus operator in order to enable said processor bus operator to execute said instruction code.

Claim 8

The terminal as claimed in claim 3 wherein said micro-instruction decoder includes a class-of-instruction decoder for determining test, literal load, and data transfer instructions and generating a control level representing the determined instruction.

Claim 9

A programmable display terminal comprising: a. means for generating instruction codes; b. single data bus means; c. a single-bus computer operatively connected to said instruction codes generating means for processing said instruction codes, said instruction codes applied to said single-bus computer via said single data bus means, said single-bus computer including i. a processor bus operator for processing data, ii. a micro-instruction decoder operatively connected to said processor bus operator, and iii. a read-only memory operatively connected to said micro-instruction decoder and said instruction codes generating means; and d. display means operatively connected to said single-bus computer for presenting the processed instruction codes, said processed instruction codes applied to said display means via said single data bus means.

Claim 10

A programmable display terminal comprising: a. means for generating instruction codes; b. single data bus means; c. a single-bus computer operatively connected to said instruction codes generating means for processing said instruction codes, said instruction codes applied to said single-bus computer via said single data bus means, said single-bus computer including i. a processor bus operator for processing data, ii. a micro-instruction decoder operatively connected to said processor bus operator, and iii. a read-only memory operatively connected to said micro-instruction decoder and said instruction codes generating means; and d. display means operatively connected to said single-bus computer for presenting the processed instruction codes, said processed instruction codes applied to said display means via said single data bus means.

Claim 11

The programmable terminal as claimed in claim 7 including: a. a source bus and a destination bus defining a single data bus; b. said processor bus operator accepting data from said single data bus, modifying said data in accordance with a computationally complete instruction set defined by said micro-instruction decoder and read-only memory; c. said micro-instruction decoder converting and decoding the data stored in said read-only memory into signals required by said processor bus operator; d. said processed data generated by said processor bus operator being applied to said display via said single data bus.

Claim 12

The programmable teraminal as claimed in claim 8 including read-only micro-data memory means operatively connected to said single data bus, said read-only micro-data memory means being used for code conversion in adapting the terminal to several different communications codes.

Claim 13

The programmable terminal as claimed in claim 8 including a control bus operatively connected to said micro-instruction decoder for addressing and controlling said micro-instruction decoder.

Claim 14

The programmable terminal as claimed in claim 10 including read/write microprogrammed memory means communicating with said single data bus and said control bus, said read/write microprogrammed memory means operating to establish micro-instruction programs.

Claim 15

The programmable terminal as claimed in claim 10 including read/write macroprogram memory means communicating with said source bus, said destination bus, and said control bus, said read/write macroprogrammed memory means operating to program the terminal using macro-instructions.

Claim 16

A microprogrammed terminal Comprising: a. a source bus to which data is supplied; b. a destination bus from which data is received, said source bus and said destination bus defining a single data bus; c. a control bus for addressing and controlling subsystems of the terminal; d. means for generating instruction codes, said instruction code generating means operatively connected to said single data bus; e. a single-bus processor operatively connected to said single data bus, said single-bus processor accepting data from said single data bus and applying processed data to said single data bus; f. a micro-instruction decoder operatively connected to said single-bus processor and said control bus; g. a microprogrammed read-only memory operatively connected to said single data bus and said micro-instruction decoder; h. timing and format generator means operatively connected to said single data and control buses; i. a read/write microprogrammed memory operatively connected to said single data bus; j. a read/write macroprogrammed memory operatively connected to said single data bus; k. display means operatively connected to said timing and format generator means for presenting said instruction codes; l. serial refresh memory means operatively connected to said display means for storing a complete page of text which is displayed by said terminal; m. memory buffer register means operatively connected to said serial refresh memory means, said memory buffer register means operating as a source and destination of data; n. character generator means operatively connected to said display means and timing and format generator means, said character generator means creating the specific alphanumeric symbol presented on said display means, said character generator means acting as a destination of data from said memory buffer register means on a cycle steal means basis.

Claim 17

A microprogrammed terminal Comprising: a. a source bus to which data is supplied; b. a destination bus from which data is received, said source bus and said destination bus defining a single data bus; c. a control bus for addressing and controlling subsystems of the terminal; d. means for generating instruction codes, said instruction code generating means operatively connected to said single data bus; e. a single-bus processor operatively connected to said single data bus, said single-bus processor accepting data from said single data bus and applying processed data to said single data bus; f. a micro-instruction decoder operatively connected to said single-bus processor and said control bus; g. a microprogrammed read-only memory operatively connected to said single data bus and said micro-instruction decoder; h. timing and format generator means operatively connected to said single data and control buses; i. a read/write microprogrammed memory operatively connected to said single data bus; j. a read/write macroprogrammed memory operatively connected to said single data bus; k. display means operatively connected to said timing and format generator means for presenting said instruction codes; l. serial refresh memory means operatively connected to said display means for storing a complete page of text which is displayed by said terminal; m. memory buffer register means operatively connected to said serial refresh memory means, said memory buffer register means operating as a source and destination of data; n. character generator means operatively connected to said display means and timing and format generator means, said character generator means creating the specific alphanumeric symbol presented on said display means, said character generator means acting as a destination of data from said memory buffer register means on a cycle steal means basis.

Claim 18

The terminal as claimed in claim 13 wherein said micro-instruction decoder includes: a. a destination address buffer operatively connected to said read-only memory; b. a destination address outgating operatively connected to said destination address buffer; c. wired OR circuit means operatively connected to said destination address outgating; d. address bus drivers operatively connected to said wired OR circuit means; e. class-of-instruction decoder means operatively connected to said destination address buffer and destination address outgating; f. source address ingating means operatively connected to said read-only memory and wired OR circuit means; g. literal load ingating means operatively connected to said read-only memory; h. test logic means operatively connected to said literal load ingating means; and i. skip logic means operatively connected to said class-of-instruction decoder means and test logic means.

Claim 19

A programmable display terminal comprising: a. source bus means for accepting instruction codes; b. destination bus means from which data is received, said source bus means and said destination bus means defining single data bus means; c. control bus means from which addressing data is supplied; d. means operatively connected to said single data bus means for generating instruction codes; e. a single-bus computer operatively connected to said single data bus means and control bus means for processing said instruction codes; and f. display means operatively connected to said single data bus means for presenting the processed instruction codes.

Claim 20

A programmable display terminal comprising: a. source bus means for accepting instruction codes; b. destination bus means from which data is received, said source bus means and said destination bus means defining single data bus means; c. control bus means from which addressing data is supplied; d. means operatively connected to said single data bus means for generating instruction codes; e. a single-bus computer operatively connected to said single data bus means and control bus means for processing said instruction codes; and f. display means operatively connected to said single data bus means for presenting the processed instruction codes.

Claim 21

The display terminal as claimed in claim 15 wherein said single-bus computer includes: a. a single-bus processor operatively connected to said single data bus means, said single-bus processor accepting data from said single data bus means and applying processed data to said single data bus means; b. a micro-instruction decoder operatively connected to said control bus means and single-bus processor; and c. microprogRammed read-only memory operatively connected to said single data bus means and said micro-instruction decoder; d. said processor bus operator accepting data from said single data bus means, modifying said data in accordance with a computationally complete instruction set as specified by said micro-instruction decoder and returning the processed data to said destination bus means; e. said microprogrammed read-only memory communicating with said single data bus means, said microprogrammed read-only memory handling all permanent processing, data transfer, and diagnostic tests of the terminal.

Claim 22

The display terminal as claimed in claim 16 wherein said single-bus computer includes timing and format generator means operatively connected to said single data and control bus means.

Claim 23

The display terminal as claimed in claim 17 including serial refresh memory means operatively connected to said display means for storing a complete page of text which is displayed by said terminal on said display means.

Claim 24

The display terminal as claimed in claim 18 including memory buffer register means operatively connected to said serial refresh memory means, said memory buffer register means operating as a source and destination of data.

Claim 25

The display terminal as claimed in claim 19 including character generator means operatively connected to said display means and said single data bus means, said character generator means creating the specific alphanumeric characters presented on said display means, said character generator means acting as a destination of data from said memory buffer register means.

Claim 26

The display terminal as claimed in claim 15 including read-only micro-data memory means operatively connected to said single data bus means, said read-only micro-data memory means being used for code conversion in adapting the terminal to several different communications codes.

Claim 27

The display terminal as claimed in claim 15 including: a. read-write microprogrammed memory means communicating with said single data bus means and said control bus means, said read/write microprogrammed memory means operating to establish micro-instruction programs; and b. read/write macroprogrammed means communicating with said single data bus means and said control bus means, said read/write macrorogrammed memory means operating to program the terminal using macro-instructions.