US3774079A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Monolithically fabricated tranistor circuit with multilayer conductive patterns
Assignee: International Business Machines Corp
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Filing: 1971-06-25
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Granted: 1973-11-20
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Expires: 1991-06-25
Abstract
Abstract During the processing of monolithically fabricated semiconductor circuits, the entire surface of a chip or wafer is covered completely with aluminum or another suitable conductive pattern material. The surface of the wafer is then selectively masked for the purpose of isolating conductive patterns from each other. Instead of the usual process of removing unwanted portions of the aluminum surface, the aluminum is anodized in an electrolytic bath to change the unmasked portions of the aluminum pattern to aluminum oxide. In this way, the conductive patterns are isolated from each other by the aluminum oxide rather than by removal of aluminum and covering of the surface with sputtered quartz. By repeating the steps of evaporating a layer of aluminum over the wafer and then selectively masking and anodizing the unmasked areas, a multilayer interconnection pattern can be formed without the requirement of sputtered quartz between the various layers. With this method, metal conductor crossovers are easily produced thereby obviating the need for crossunders within the semiconductor material. It has been found that the aluminum oxide formed by anodization within the electrolytic bath is not subject to some of the pin hole problems that exist with respect to the sputtered quartz thereby eliminating part of the problems that has existed to inhibit the widespread introduction of multilayer conductive patterns in the integrated circuit art. A problem, which has existed with multilayer conductive patterns is also obviated by the improved method, i.e. the ability to make reliable electrical connections between the aluminum (or other conductor) of two different interconnection layers, has been extremely difficult or costly with known earlier techniques.
Inventors
- 👤 J Zechman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 10:44
CPC Classifications
H; H10; H10P; H10P14/00; H10P14/60; H10P14/69; H10P14/692; H10P14/6938; H10P14/6939; H10P14/69391; H10P14/63; H10P14/6302; H10P14/6324; H10W; H10W20/00; H10W20/40
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
209 words
In a structure of the type in which semiconductor circuit components are formed in one face of the substrate of a single semiconductor chip by a monolithic fabrication technique, an electrical interconnection means for said components comprising metalization patterns formed in each of at least three layers one above the other on said fAce of said chip, each layer of metalization patterns including a single metallic layer, having electrolytically anodized portions to electrically isolate other conductive portions thereof from each other, at least certain of said conducting portions in an intermediate one of said layers electrically and physically connected to selected conductive portions in both of a pair of layers above and below said intermediate layer to selectively interconnect said patterns in a predetermined manner, certain of said patterns being electrically and physically connected to said components, a first conductive pattern in one layer of said pair, a second conductive pattern in the other layer of said pair and aligned in juxtaposed relation with said first conductive pattern, and means including an additional pair of conductive patterns in said intermediate layer, each physically and electrically connected to said second conductive pattern and electrically isolated from said first conductive pattern, to form an electrical bypass around said first conductive pattern.
Claim 2
Dependent Claim
209 words
In a structure of the type in which semiconductor circuit components are formed in one face of the substrate of a single semiconductor chip by a monolithic fabrication technique, an electrical interconnection means for said components comprising metalization patterns formed in each of at least three layers one above the other on said fAce of said chip, each layer of metalization patterns including a single metallic layer, having electrolytically anodized portions to electrically isolate other conductive portions thereof from each other, at least certain of said conducting portions in an intermediate one of said layers electrically and physically connected to selected conductive portions in both of a pair of layers above and below said intermediate layer to selectively interconnect said patterns in a predetermined manner, certain of said patterns being electrically and physically connected to said components, a first conductive pattern in one layer of said pair, a second conductive pattern in the other layer of said pair and aligned in juxtaposed relation with said first conductive pattern, and means including an additional pair of conductive patterns in said intermediate layer, each physically and electrically connected to said second conductive pattern and electrically isolated from said first conductive pattern, to form an electrical bypass around said first conductive pattern.
Claim 3
Dependent Claim
53 words
The structure set forth in claim 1, wherein the patterns in the layer immediately adjacent said one face form the physical and electrical connections to all of said components, and wherein the patterns in the layer furthest from said one face form all of the electrical connections to circuits external to the chip.
Claim 4
Dependent Claim
55 words
The structure set forth in claim 2 further comprising an insulation layer interposed between said one face of said substrate and said layer of metalization patterns immediately adjacent said one face, and apertures formed in said insulation layer filled with portions of the last-mentioned metalization patterns for making said electrical connections to said circuit components.
Claim 5
Dependent Claim
22 words
The structure set forth in claim 1 wherein said second and additional conductive patterns form an overpass around said first conductive patterns.
Claim 6
Dependent Claim
22 words
The structure set forth in claim 1 wherein said second and additional conductive patterns form an underpass around said first conductive patterns.
Claim 7
Dependent Claim
53 words
The structure set forth in claim 1 wherein the last-mentioned means further comprises a further pair of conductive patterns in said one layer of said pair electrically isolated from said first conductive pattern and each further pattern being physically and electrically connected to a respective one of said additional pair of conductive patterns.
Claim 8
Dependent Claim
272 words
In a structure of the type in which semiconductor circuit components are formed in one face of the substrate of a single semiconductor chip by a monolithic fabrication technique, an electrical interconnection means for said components comprising metalization patterns formed in each of at least three layers one above the other on said face of said chip, each layer of metalization patterns including a single metallic layer, having electrolytically anodized portions to electrically isolate other conductive portions thereof from each other, at least certain of said conducting portions in an intermediate one of said layers electrically and physically connected to selected conductive portions in both of a pair of layers above and below said intermediate layer to selectively interconnect said patterns in a predetermined manner, certain of said patterns being electrically and physically connected to said components, first elongated parallel conductive patterns in one layer of said pair, second elongated parallel conductive patterns in the other layer of said pair, conductive patterns in said intermediate layer selectively interconnecting patterns in said one and other layers, means including respective ones of said first patterns and additional pairs of conductive patterns in said intermediate layer, each latter pair physically and electrically connected to one of said first patterns and electrically isolated from a selected second pattern, to form electrical bypasses arouNd said selected second patterns, and means including respective ones of said second patterns and additional pairs of conductive patterns in said intermediate layer, each latter pair physically and electrically connected to one of said second patterns and electrically isolated from a selected first pattern, to form electrical bypasses around said selected first patterns.
Claim 9
Dependent Claim
272 words
In a structure of the type in which semiconductor circuit components are formed in one face of the substrate of a single semiconductor chip by a monolithic fabrication technique, an electrical interconnection means for said components comprising metalization patterns formed in each of at least three layers one above the other on said face of said chip, each layer of metalization patterns including a single metallic layer, having electrolytically anodized portions to electrically isolate other conductive portions thereof from each other, at least certain of said conducting portions in an intermediate one of said layers electrically and physically connected to selected conductive portions in both of a pair of layers above and below said intermediate layer to selectively interconnect said patterns in a predetermined manner, certain of said patterns being electrically and physically connected to said components, first elongated parallel conductive patterns in one layer of said pair, second elongated parallel conductive patterns in the other layer of said pair, conductive patterns in said intermediate layer selectively interconnecting patterns in said one and other layers, means including respective ones of said first patterns and additional pairs of conductive patterns in said intermediate layer, each latter pair physically and electrically connected to one of said first patterns and electrically isolated from a selected second pattern, to form electrical bypasses arouNd said selected second patterns, and means including respective ones of said second patterns and additional pairs of conductive patterns in said intermediate layer, each latter pair physically and electrically connected to one of said second patterns and electrically isolated from a selected first pattern, to form electrical bypasses around said selected first patterns.
Claim 10
Dependent Claim
169 words
In a structure of the type in which semiconductor circuit components are formed in one face of the substrate of a single semiconductor chip, an electrical interconnection means for said components, comprising metalization patterns formed in each of at least three layers one above the other on said face of said chip, each layer of metalization patterns including a single metallic layer, having electrolytically anodized portions to electrically isolate ther conductive portions thereof from each other, conducting portions in an intermediate one of said layers electrically and physically connected to selected conductive portions in a pair of layers above and below said intermediate layer to selectively interconnect said patterns in a predetermined manner, certain of said patterns being electrically and physically connected to said components, the patterns in the layer immediately adjacent said one face forming the physical and electrical connections to all of said components, and the patterns in the layer furthest from said one face forming all of the electrical connections to circuits external to said chip.
Claim 11
Dependent Claim
169 words
In a structure of the type in which semiconductor circuit components are formed in one face of the substrate of a single semiconductor chip, an electrical interconnection means for said components, comprising metalization patterns formed in each of at least three layers one above the other on said face of said chip, each layer of metalization patterns including a single metallic layer, having electrolytically anodized portions to electrically isolate ther conductive portions thereof from each other, conducting portions in an intermediate one of said layers electrically and physically connected to selected conductive portions in a pair of layers above and below said intermediate layer to selectively interconnect said patterns in a predetermined manner, certain of said patterns being electrically and physically connected to said components, the patterns in the layer immediately adjacent said one face forming the physical and electrical connections to all of said components, and the patterns in the layer furthest from said one face forming all of the electrical connections to circuits external to said chip.
Claim 12
Dependent Claim
81 words
The structure set forth in claim 8 further comprising a first conductive pattern in one layer of said pair, as second conductive pattern in the other layer of said pair and aligned in juxtaposed relation with said first conductive pattern, and means including an additional pair of conductive patterns in said intermediate layer, each physically and electrically connected to said second conductive pattern and electrically isolated from said first conductive pattern, to form an electrical bypass around said first conductive pattern.
Claim 13
Dependent Claim
53 words
The structure set forth in claim 9 wherein the last-mentioned means further comprises a further pair of conductive patterns in said one layer of said pair electrically isolated from said first conductive pattern and each further pattern being physically and electrically connected to a respective one of said additional pair of conductive patterns.
Claim 14
Dependent Claim
260 words
In a structure of the type in which semiconductor circuit components are formed in one face of the substrate of a single semiconductor chip, an electrical interconnection means for said components, comprising metalization patterns formed in each of at least three layers one above the other on said face of said chip, each layer of metalization patterns including a single metallic layer, having electrolytically anodized portions to electrically isolate other conductive portions thereof from each other, conducting portions in an intermediate one of said layers electrically and physically connected to selected conductive portions in a pair of layers above and below said intermediate layer to selectively interconnect said patterns in a predetermined manner, certain of said patterns being electrically and physically connected to said components, first elongated parallel conductive patterns in one layer of said pair, second elongated parallel conductive patterns in the other layer of said pair, conductive patterns in said intermediate layer selectively interconnecting patterns in said one and other layers, means including respective ones of said first patterns and additional pairs of conductive patterns in said intermediate layer, each latter pair physically and electrically connected to one of said first patterns and electrically isolated from a selected second pattern, to form electrical bypasses around said selected second patterns, and means including respective ones of said second patterns and additionAl pairs of conductive patterns in said intermediate layer, each latter pair physically and electrically connected to one of said second patterns and electrically isolated from a selected first pattern, to form electrical bypasses around said selected first patterns.
Claim 15
Dependent Claim
260 words
In a structure of the type in which semiconductor circuit components are formed in one face of the substrate of a single semiconductor chip, an electrical interconnection means for said components, comprising metalization patterns formed in each of at least three layers one above the other on said face of said chip, each layer of metalization patterns including a single metallic layer, having electrolytically anodized portions to electrically isolate other conductive portions thereof from each other, conducting portions in an intermediate one of said layers electrically and physically connected to selected conductive portions in a pair of layers above and below said intermediate layer to selectively interconnect said patterns in a predetermined manner, certain of said patterns being electrically and physically connected to said components, first elongated parallel conductive patterns in one layer of said pair, second elongated parallel conductive patterns in the other layer of said pair, conductive patterns in said intermediate layer selectively interconnecting patterns in said one and other layers, means including respective ones of said first patterns and additional pairs of conductive patterns in said intermediate layer, each latter pair physically and electrically connected to one of said first patterns and electrically isolated from a selected second pattern, to form electrical bypasses around said selected second patterns, and means including respective ones of said second patterns and additionAl pairs of conductive patterns in said intermediate layer, each latter pair physically and electrically connected to one of said second patterns and electrically isolated from a selected first pattern, to form electrical bypasses around said selected first patterns.
Claim 16
Dependent Claim
195 words
In a structure of the type in which circuit components are carried by a mounting element, an electrical interconnection means on said element for said components, comprising metalization patterns formed in each of at least three layers one above the other on one face of said element, each layer of metalization patterns including a single metallic layer, having electrolytically anodized portions to electrically isolate other conductive portions thereof from each other, conducting portions in an intermediate one of said layers electrically and physically connected to selected conductive portions in a pair of layers above and below said intermediate layer to selectively interconnect said patterns in a predetermined manner, said metalization patterns in at least one of said layers electrically connected to said components, a first conductive pattern in one layer of said pair, a second conductive pattern in the other layer of said pair and aligned in juxtaposed relation with said first conductive pattern, and means including an additional pair of conductive patterns in said intermediate layer, each physically and electrically connected to said second conductive pattern and electrically isolated from said first conductive pattern, to form an electrical bypass around said first conductive pattern.
Claim 17
Dependent Claim
195 words
In a structure of the type in which circuit components are carried by a mounting element, an electrical interconnection means on said element for said components, comprising metalization patterns formed in each of at least three layers one above the other on one face of said element, each layer of metalization patterns including a single metallic layer, having electrolytically anodized portions to electrically isolate other conductive portions thereof from each other, conducting portions in an intermediate one of said layers electrically and physically connected to selected conductive portions in a pair of layers above and below said intermediate layer to selectively interconnect said patterns in a predetermined manner, said metalization patterns in at least one of said layers electrically connected to said components, a first conductive pattern in one layer of said pair, a second conductive pattern in the other layer of said pair and aligned in juxtaposed relation with said first conductive pattern, and means including an additional pair of conductive patterns in said intermediate layer, each physically and electrically connected to said second conductive pattern and electrically isolated from said first conductive pattern, to form an electrical bypass around said first conductive pattern.
Claim 18
Dependent Claim
53 words
The structure set forth in claim 12 wherein the last-mentioned means further comprises a further pair of conductive patterns in said one layer of said pair electrically isolated from said first conductive pattern and each further pattern being physically and electrically connected to a respective one of said additional pair of conductive patterns.
Claim 19
Dependent Claim
258 words
In a structure of the type in which circuit components are carried by a mounting element, an electrical interconnection means on said element for said components, comprising metalization patterns formed in each of at least three layers one above the other on one face of said element, each layer of metalization patterns including a single metallic layer, having electrolytically anodized portions to electrically isolate other conductive portions thereof from each other, conducting portions in an intermediate one of said layers electrically and physically connected to selected conductive portions in a pair of layers above and below said intermediate layer to selectively interconnect said patterns in a predetermined manner, said metalization patterns in at least one of said layers electrically connected to said components, first elongated parallel conductive patterns in one layer of said pair, second elongated parallel conductive patterns in the other layer of said pair, conductive patterns in said intermediate layer selectively interconnecting patterns in said one and other layers, means including respective ones of said first patterns and additional pairs of conductive patterns in said intermediate layer, each latter pair physically and electrically connected to one of said first patterns and electrically isolated from a selected second pattern, to form electrical bypasses around said selected second patterns, and means including respective ones of said second patterns and additional pairs of conductive patterns in said intermediate layer, each latter pair physically and electrically connected to one of said second patterns and electrically isolated from a selected first pattern, to form electrical bypasses around said selected first patterns.
Claim 20
Dependent Claim
258 words
In a structure of the type in which circuit components are carried by a mounting element, an electrical interconnection means on said element for said components, comprising metalization patterns formed in each of at least three layers one above the other on one face of said element, each layer of metalization patterns including a single metallic layer, having electrolytically anodized portions to electrically isolate other conductive portions thereof from each other, conducting portions in an intermediate one of said layers electrically and physically connected to selected conductive portions in a pair of layers above and below said intermediate layer to selectively interconnect said patterns in a predetermined manner, said metalization patterns in at least one of said layers electrically connected to said components, first elongated parallel conductive patterns in one layer of said pair, second elongated parallel conductive patterns in the other layer of said pair, conductive patterns in said intermediate layer selectively interconnecting patterns in said one and other layers, means including respective ones of said first patterns and additional pairs of conductive patterns in said intermediate layer, each latter pair physically and electrically connected to one of said first patterns and electrically isolated from a selected second pattern, to form electrical bypasses around said selected second patterns, and means including respective ones of said second patterns and additional pairs of conductive patterns in said intermediate layer, each latter pair physically and electrically connected to one of said second patterns and electrically isolated from a selected first pattern, to form electrical bypasses around said selected first patterns.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-11-19 | 1977-05-21 | 1977-11-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-11-19 | 1981-05-21 | 1981-11-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-11-19 | 1985-05-21 | 1985-11-20 | $7700.00 | Window Closed / Lapsed |