Method and means for interconnecting conductors on different metalization pattern levels on monolithically fabricated integrated circuit chips

Claim 2

The structure of claim 1 wherein said first diffused region has a resistivity in the order of 4 to 20 ohms per square.

Claim 3

In a structure of the type in which a plurality of bipolar transistor circuits are formed in the epitaxial layer on one face of the substrate of a single semiconductor chip by a monolithic fabrication technique, in which first and second metalization patterns are formed in two electrically isolated layers, one above the other, on said face of the chip, and, in which the circuits are electrically interconnected by means including the metalization patterns, wherein at least certain of the interconnection means are each characterized by a first diffused low resistivity region formed in said epitaxial layer, a second diffused region formed in said epitaxial layer electrically isolating the first diffused region from the remainder of the epitaxial layer, an interconnection portion of the first metalization pattern of one layer and an interconnection portion of the second metalization pattern of the other layer alloyed together with respective contiguous parts of said first diffused region to form an electrical connection between said pattern portions, said interconnection portion of the second metalization pattern overlying and engaging said interconnection portion of the first metalization pattern.

Claim 4

The structure as defined in claim 4 wherein each of said first diffused regions is formed simultaneously with transistor emitter regions, and wherein each of said second diffused regions is formed simultaneously with transistor base regions.

Claim 5

In a structure of the type in which transistor circuits are formed in one face of the substrate of a single semiconductor chip by a monolithic fabrication technique, in which metalization patterns are formed in two electrically isolated layers, one above the other on said face of the chip, and in which the circuits are electrically interconnected by means including the metalization patterns, wherein at least certain of the interconnection means are each characterized by a low resistivity diffusion region formed in said face and electrically isolated from the remainder of the substrate, and a portion of the pattern of one layer and a portion of the pattern of the other layer engaging each other and alloyed together with contiguous parts of said low resistivity region to form a low impedance electrical connection between said pattern portions.

Claim 6

In a method of the type including the steps of growing an epitaxial layer on one face of the substrate of a single semiconductor chip, forming a plurality of bipolar transistor circuits in the epitaxial layer, forming first and second metalization patterns in two electrically isolated layers, one above the other, on the epitaxial layer, and electrically interconnecting the circuits by way of the metalization patterns, the improvement being a method of reliably interconnecting adjacent portions of the upper and lower metalization patterns comprising the steps of forming an isolated low resistivity region in the epitaxial layer in each position where an interconnection is to be made between metalization patterns, alloying selected portions of the lower metalization pattern to parts of respective ones of said low resistivity regions, and alloying selected portions of the upper metalization pattern to the remaining parts of respective ones of said low resistivity regions to make a reliable contact between the patterns by way of each low resistivity region.

Claim 7

The method of claim 7 further characterized by the steps of forming the low resistivity regions simultaneously with the formation of the transistor emitter regions, forming an isolation region of opposite conductivity type around each low resistivity region simultaneously with the formation of the transistor base regions.