Threshold logic three-input adder

Claim 2

A threshold logic adder circuit comprising first and second busses; means for converting each of five information bits into a unit of current conducted alternatively through the first or the second bus; means responsive to current in the first and second busses for producing potentials thereon; means responsive to the potential on the first bus for steering selectively four units, two units, or no units of current through the second bus; and means for comparing the potential on the second bus with a reference potential.

Claim 3

An adder circuit in accordance with claim 1 wherein the comparing means includes a bistable circuit being constrained to a first stable state when at least five units of current are conducted in the second bus and being constrained to a second state when less than five units of current are conducted in the second bus.

Claim 4

An adder circuit in accordance with claim 2 wherein the means selectively steering current includes first and second current steering circuits; the first steering circuit steers two units of current through the second bus only when at least four units of current are conducted in the first bus; and the second steering circuit steers two units of current through the second bus only when at least two units of current are conducted in the first bus.

Claim 5

An adder circuit in accordance with claim 3 wherein the converting means include five separate storage-processor elements having complementary outputs connected respectively to the first and second busses; and the comparing means comprises a further storage-processor element having a first input connected to the second bus and a reference potential applied to a second input.

Claim 6

An adder circuit in accordance with claim 1 wherein control means apply a pair of complementary drive signals to all of the storage-processor elements for synchronizing operation of the elements.

Claim 7

A threshold logic adder comprising carry and sum busses; storage-processor means for storing three addend-word bits and two carry-bits and for selectively directing five units of current through the carry bus or through the sum bus depending upon the values of the addendword bits and the carry-bits; means responsive to current conducted in the carry and sum busses for producing potentials thereon; a first steering circuit responsive to the potential on the carry bus and to a reference potential for steering two units of current through the sum bus only when at least four units of current are conducted in the carry bus; a second steering circuit responsive to the potential on the carry bus and to another reference potential for steering two units of current through the sum bus only when at least two units of current are conducted in the carry bus; and a sum storage-processor element responsive to the potential on the sum bus and to a predetermined reference potential is constrained to a first stable state when at least five units of current are conducted in the sum bus and is constrained to a second stable state when less than five units of current are conducted in the sum bus.

Claim 8

A threshold logic adder comprising carry and sum busses; storage-processor means for storing three addend-word bits and two carry-bits and for selectively directing five units of current through the carry bus or through the sum bus depending upon the values of the addendword bits and the carry-bits; means responsive to current conducted in the carry and sum busses for producing potentials thereon; a first steering circuit responsive to the potential on the carry bus and to a reference potential for steering two units of current through the sum bus only when at least four units of current are conducted in the carry bus; a second steering circuit responsive to the potential on the carry bus and to another reference potential for steering two units of current through the sum bus only when at least two units of current are conducted in the carry bus; and a sum storage-processor element responsive to the potential on the sum bus and to a predetermined reference potential is constrained to a first stable state when at least five units of current are conducted in the sum bus and is constrained to a second stable state when less than five units of current are conducted in the sum bus.

Claim 9

An adder in accordance with claim 6 wherein a first storage-processor element for storing one of the two carry-bits responds to the potential on the carry bus and to a reference potential, is constrained to a first stable state when at least four units of current are conducted in the carry bus, and is constrained to a second stable state when less than four units of current are conducted in the carry bus; and a second storage-processor element for storing one of the two carry-bits responds to the potential on the carry bus and to a reference potential, is constrained to a first stable state when at least two units of current are conducted in the carry bus, and is constrained to a second stable state when less than two units of current are conducted in the carry bus.

Claim 10

An adder in accorDance with claim 7 wherein control means apply a pair of complementary drive signals to all of the storage-processor means for synchronizing their operation.

Claim 13

An m input, where m is greater than 2, threshold logic adder comprising carry and sum busses; means for storing m input-bits, each from a corresponding order of m addend-words; means for storing m-1 carry-bits, each generated by a summation of bits of a next lower order of significance in the addend-words; the 2m-1 storing means being arranged for directing units of current through the carry and sum busses alternatively, depending upon the value of the bits stored; means for writing m-1 new carry-bits in the carry-bit storing means, each new carry-bit being related to a different number of units of current conducted through the carry bus; means responsive to the number of units of current conducted through the carry bus for selectively steering a different number of units of current through the sum bus for every new carry-bit to be written; and means for storing a sum-bit simultaneously with the storing of the m-1 new carry-bits, the sum-bit being related to a predetermined number of units of current conducted through the sum bus.

Claim 14

An m input, where m is greater than 2, threshold logic adder comprising carry and sum busses; means for storing m input-bits, each from a corresponding order of m addend-words; means for storing m-1 carry-bits, each generated by a summation of bits of a next lower order of significance in the addend-words; the 2m-1 storing means being arranged for directing units of current through the carry and sum busses alternatively, depending upon the value of the bits stored; means for writing m-1 new carry-bits in the carry-bit storing means, each new carry-bit being related to a different number of units of current conducted through the carry bus; means responsive to the number of units of current conducted through the carry bus for selectively steering a different number of units of current through the sum bus for every new carry-bit to be written; and means for storing a sum-bit simultaneously with the storing of the m-1 new carry-bits, the sum-bit being related to a predetermined number of units of current conducted through the sum bus.