Data handling devices for radix {37 n{30 2{38 {0 operation

Claim 2

A data-handling element comprising: a. a plurality of switch means, b. input means for accepting a plurality of parallel binary input signals and for operating said plurality of switch means in response thereto, each one of said switch means coupled to a different one of said input signals, said plurality of switch means each having a first and second output, c. a first internal node means arranged to be switched to each one of at least three predetermined levels of stability in response to the levels of said parallel binary input signals, said first internal node means coupled to said first output of each of said switch means, d. a second internal node means arranged to be switched to each one of at least two predetermined levels of stability in response to the levels of said parallel binary input signals, said second internal node means coupled to said second output of each of said switch means, and e. output means for generating at least one binary output signal in response to the relative levels of said first and second internal node means; wherein said output means comprises first, second, third and fourth transistor means, the base of said first and second transistor means being coupled to said first and second internal node means respectively, the emitters of said first and second transistor means being connected together, the base of said third transistor means being coupled to the collector of said second transistor means, and the base of said fourth transistor means being coupled to said first internal node means.

Claim 3

A data-handling element according to claim 1 wherein said element comprises an integrated circuit device.

Claim 4

A data-handling element according to claim 1 wherein, A. said input means is adapted to accept first, second and third parallel binary input signals, B. said first internal node means is adapted to be switched to one of four predetermined levels of stability, C. said second internal node means is adapted to be switched to one of said four predetermined levels of stability, D. said four predetermined levels of stability comprising, in order of magnitude, a first extreme level, a first intermediate level, a second intermediate level, and a second extreme level, E. said switch means causing said first and second internal node means respectively be at said first and said second extreme levels when said input signals are all at a first one of the two available binary levels and respectively to be at said second and said first extreme levels when said input signals are all at the second one of the two binary levels, and causing said first and second internal node means respectively to be at said first and said second intermediate levels when one and only one of said input signals is at said second one of the two binary levels and respectively to be at said second and said first intermediate levels when one and only one of said input signals is at said first one of the two binary levels, and F. the collector of said first transistor means being responsive to the presence of either said first extreme level or said first intermediate level on said first internal node means and the respectively corresponding presence of either said second extreme level or said second intermediate level on said second internal node means to generate a first binary output signal at said first one of said two available binary levels, said collector of said first transistor means also being responsive to the presence of either said second intermediate leveL or said second extreme level on said first internal node means and the respectively corresponding presence of either said first intermediate level or said first extreme level on said second internal node means to generate said first binary output signal at said second one of the two binary levels.

Claim 5

A data-handling element according to claim 3 wherein the collector of said fourth transistor is responsive to the presence of either said first extreme level or said second intermediate level on said first node means to generate a second binary output signal at said first one of said two available binary levels, said collector of said fourth transistor also being responsive to the presence of either said first intermediate level or said second extreme level on said first node means to generate said second binary output signal at said second one of said two available binary levels.

Claim 6

A data-handling element comprising: a. a plurality of switch means, b. input means for accepting a plurality of parallel binary input signals and for operating said plurality of switch means in response thereto, each one of said switch means coupled to a different one of said input signals, said plurality of switch means each having a first and second output, c. a first internal node means arranged to be switched to each one of at least three predetermined levels of stability in response to the levels of said parallel binary input signals, said first internal node means coupled to said first output of each of said switch means, d. a second internal node means arranged to be switched to each one of at least two predetermined levels of stability in response to the levels of said parallel binary input signals, said second internal node means coupled to said second output of each of said switch means, and e. output means for generating at least one binary output signal in response to the relative levels of said first and second internal node means, wherein said output means comprises first, second, and third transistor means, the bases of said first and second transistor means being coupled to said first and second internal node means respectively, the emitters of said first, second and third transistor means being coupled to a common point and the base of said third transistor means being coupled to a reference voltage.

Claim 7

A data-handling element comprising: a. a plurality of switch means, b. input means for accepting a plurality of parallel binary input signals and for operating said plurality of switch means in response thereto, each one of said switch means coupled to a different one of said input signals, said plurality of switch means each having a first and second output, c. a first internal node means arranged to be switched to each one of at least three predetermined levels of stability in response to the levels of said parallel binary input signals, said first internal node means coupled to said first output of each of said switch means, d. a second internal node means arranged to be switched to each one of at least two predetermined levels of stability in response to the levels of said parallel binary input signals, said second internal node means coupled to said second output of each of said switch means, and e. output means for generating at least one binary output signal in response to the relative levels of said first and second internal node means, wherein said output means comprises first, second, and third transistor means, the bases of said first and second transistor means being coupled to said first and second internal node means respectively, the emitters of said first, second and third transistor means being coupled to a common point and the base of said third transistor means being coupled to a reference voltage.

Claim 8

An EXCLUSIVE OR logic element according to claim 5 wherein, A. said input means is adapted to accept first and second parallel binary input signals, B. said first internal node means is adapted to be switched to one of three predetermined levels of stability, C. said second internal node means is adapted to be switched to one of said three predetermined levels of stability, D. said three predetermined levels of stability comprising a first extreme level, an intermediate level and a second extreme level, E. said switch means causing both said first and said second internal node means to be at said intermediate level of stability when said binary input signals are at the same binary level, and causing said first and said second node means to each be at a different one of said first and said second extreme levels of stability when said first binary input signal has a different value from said second binary input signal, and, F. said output means being responsive to the presence of said intermediate levels of stability on both said first and said second internal node means for generating said binary output at a first one of the two available binary levels and being responsive to the presence of said first extreme level of stability on either of said internal node means to generate said binary output at a second one of the two available binary levels.