Data sampling apparatus

Claim 2

A data sampling apparatus, comprising: first means having a plurality of input connections for receiving a plurality of binary coded signals comprising bits in corresponding bit periods, each bit having a first value or a second value, said first means being operative to sample the bits in the bit periods of the plurality of binary coded signals received at its input connections thereby to derive sampled signals, each having a first value or a second value, and to produce a transition output signal for each transition in each binary coded signal from one of its bit values to the other of its bit values; counting means coupled to the first means and operative in response to a transition output signal produced by the first means to count through a predetermined sequence of counts, said counting means comprising: a. a plurality of shift register means each having an input connection and an output connection, the input connection of the first one of the plurality of shift register means being coupled to the first means, and the output connection of each of the plurality of shift register means, with the exception of the last one of the plurality of shift register means, being coupled to the input connection of the next shift register means; and b. logic means coupled to the plurality of shift register means and to the first means and operative when a transition output signal is produced by the first means to establish a counting mode of operation for the plurality of shift register means whereby successive combinations of output signals, corresponding to the samples of the bit present in the bit period following the transition for which the transition output signal is produced by the first means, are caused to be established at the output connections of the plurality of shift register means, said combinations of output signals representing different counts, one of said counts representing a particular point in each bit period following a transition Pg,27 for which a transition output signal is produced by the first means; detector means coupled to the output connections of the plurality of shift register means and adapted to examine the counts established at the output connections of the plurality of shift register means, said detector means being operative in response to detecting a count representing the aforesaid particular point in a bit period following a transition for which a transition output signal is produced by the first means to produce a corresponding output signal; and output means coupled to the detector means and to the first means, said output means being operative in response to an output signal produced by the detector means corresponding to a count representing the aforesaid point in a bit period to receive and store a sampled signal from the first means representing the value of the bit in said bit period.

Claim 3

A data sampling apparatus in accordance with claim 1 wherein: the logic means includes an exclusive-or logic arrangement.

Claim 4

A data sampling apparatus in accordance with claim 1 wherein: the logic means includes: a positive AND gate and a negative AND gate, each having first and second input connections coupled, respectively, to the output connection of the first one of the plurality of shift register means and to the output connection of another one of the plurality of shift register means, and each having an output connection; and a gate coupled to the output connections of the positive and negative AND gates and to the input connection of the first one of the plurality of shift register means.

Claim 5

A data sampling apparatus in accordance with claim 3 wherein: said another one of the plurality of shift register means is the last one of the plurality of shift register means.

Claim 6

A data sampling apparatus in accordance with claim 1 wherein: the detector means is operative to produce an output signal in response to detecting a count representing the center of a bit period following a transition for which a transition output signal is produced by the first means.

Claim 7

A data sampling apparatus in accordance with claim 1 wherein: said plurality of shift register means comprise stages; another one of the counts established at the output connections of the plurality of shift register means represents a second point in each bit period following a transition for which a transition output signal is produced by the first means; and said data sampling apparatus further comprises: second detector means coupled to the output connections of the plurality of shift register means and adapted to examine the counts established at the output connections of the plurality of shift register means, said second detector means being operative in response to detecting a count representing said another point in a bit period following a transition for which a transition output signal is produced by the first means to produce a corresponding output signal; and means coupled to the second detector means and to the input connections of the plurality of shift register means and operative in response to each output signal produced by the second detector means to reset the first stages of said plurality of shift register means.

Claim 8

A data sampling apparatus in accordance with claim 6 wherein: the second detector means is operative to produce an output signal in response to detecting a count representing the end of a bit period following a transition for which an output signal is produced by the first means.

Claim 9

A data sampling apparatus in accordance with claim 1 wherein the output means comprises: a bit value shift register means for receiving and storing each sampled signal from the first means in response to an output signal being produced by the detector means.

Claim 10

A data sampling apparatus in accordance with claim 8, further comprising: a bit storage shift register means operative to receive and store each Output signal produced by the first detector means synchronous with each sampled signal received and stored by the bit value shift register means.

Claim 11

A data sampling apparatus, comprising: sampling means having a plurality of input connections for receiving a plurality of binary coded signals comprising bits in corresponding bit periods, each bit having a first value or a second value, and further having an output connection means, said sampling means being operative to sample the bits in the bit periods of the plurality of binary coded signals received at its input connections and to apply the sampled signals, each having a first bit value or a second bit value, to its output connection means; sample storage means coupled to the output connection means of the sampling means and operative to receive and store therein the sampled signals applied to the output connection means of the sampling means; first detector means coupled to the sample storage means and adapted to examine the sampled signals applied to and stored in the sample storage means, said first detector means being operative in response to detecting a particular combination of sampled signals stored by the sample storage means indicating the occurrence of a transition in one of the binary coded signals from one of its bit values to the other of its bit values to produce a transition output signal; counting means coupled to the first detector means and operative in response to a transition output signal produced by the first detector means to count through a predetermined sequence of counts, said counting means comprising: a. a plurality of shift register means each having an input connection and an output connection, the input connection of the first one of the plurality of shift register means being coupled to the first detector means, and the output connection of the plurality of shift register means, with the exception of the last one of the plurality of shift register means, being coupled to the input connection of the next shift register means; and b. logic means coupled to the plurality of shift register means and to the first detector means and operative when a transition output signal is produced by the first detector means to establish a counting mode of operation for the plurality of shift register means whereby successive combinations of output signals, corresponding to the samples of the bit present in the bit period following the transition for which the transition output signal is produced by the first means, are caused to be established at the output connections of the plurality of shift register means, said combinations of output signals representing different counts, one of said counts representing the center of each bit period following a transition for which a transition output signal is produced by the first detector means; second detector means coupled to the output connections of the plurality of shift register means and adapted to examine the counts established at the output connections of the plurality of shift register means, said second detector means being operative in response to detecting a count representing the center of a bit period following a transition for which a transition output signal is produced by the first detector means to produce a corresponding output signal; and output means coupled to the second detector means and to the sample storage means, said output means being operative in response to an output signal produced by the second detector means corresponding to a count representing the center of a bit period to receive a sampled signal from the sample storage means representing the value of the bit in said bit period.

Claim 12

A data sampling apparatus, comprising: sampling means having a plurality of input connections for receiving a plurality of binary coded signals comprising bits in corresponding bit periods, each bit having a first value or a second value, and further having an output connection means, said sampling means being operative to sample the bits in the bit periods of the plurality of binary coded signals received at its input connections and to apply the sampled signals, each having a first bit value or a second bit value, to its output connection means; sample storage means coupled to the output connection means of the sampling means and operative to receive and store therein the sampled signals applied to the output connection means of the sampling means; first detector means coupled to the sample storage means and adapted to examine the sampled signals applied to and stored in the sample storage means, said first detector means being operative in response to detecting a particular combination of sampled signals stored by the sample storage means indicating the occurrence of a transition in one of the binary coded signals from one of its bit values to the other of its bit values to produce a transition output signal; counting means coupled to the first detector means and operative in response to a transition output signal produced by the first detector means to count through a predetermined sequence of counts, said counting means comprising: a. a plurality of shift register means each having an input connection and an output connection, the input connection of the first one of the plurality of shift register means being coupled to the first detector means, and the output connection of the plurality of shift register means, with the exception of the last one of the plurality of shift register means, being coupled to the input connection of the next shift register means; and b. logic means coupled to the plurality of shift register means and to the first detector means and operative when a transition output signal is produced by the first detector means to establish a counting mode of operation for the plurality of shift register means whereby successive combinations of output signals, corresponding to the samples of the bit present in the bit period following the transition for which the transition output signal is produced by the first means, are caused to be established at the output connections of the plurality of shift register means, said combinations of output signals representing different counts, one of said counts representing the center of each bit period following a transition for which a transition output signal is produced by the first detector means; second detector means coupled to the output connections of the plurality of shift register means and adapted to examine the counts established at the output connections of the plurality of shift register means, said second detector means being operative in response to detecting a count representing the center of a bit period following a transition for which a transition output signal is produced by the first detector means to produce a corresponding output signal; and output means coupled to the second detector means and to the sample storage means, said output means being operative in response to an output signal produced by the second detector means corresponding to a count representing the center of a bit period to receive a sampled signal from the sample storage means representing the value of the bit in said bit period.

Claim 13

A data sampling apparatus in accordance with claim 10 wherein: each of the bits in each bit period of each of the binary coded signals has a bit value of zero or one; each of the sampled signals derived by the sampling means and stored by the sample storage means has a bit value Of zero or one; and the first detector means is operative to produce a transition output signal in response to detecting a particular combination of sampled signals having particular values stored by the sample storage means and indicating the occurrence of a transition in one of the binary coded signals from its one value to its zero value.

Claim 14

A data sampling apparatus in accordance with claim 10 wherein: the logic means includes an exclusive-or arrangement.

Claim 15

A data sampling apparatus in accordance with claim 10 wherein: the logic means includes: a positive AND gate and a negative AND gate, each having first and second input connections coupled, respectively, to the output connection of the first one of the plurality of shift register means and to the output connection of another one of the plurality of shift register means, and each having an output connection; and a gate coupled to the output connections of the positive and negative AND gates and to the input connection of the first one of the plurality of shift register means.

Claim 16

A data sampling apparatus in accordance with claim 13 wherein: said another one of the plurality of shift register means is the last one of the plurality of shift register means.

Claim 17

A data sampling apparatus in accordance with claim 10 wherein: said plurality of shift register means comprise stages; another one of the counts established at the output connections of the plurality of shift register means represents the end of each bit period following a transition for which a transition output signal is produced by the first detector means; and said data sampling apparatus further comprises: third detector means coupled to the output connections of the plurality of shift register means and adapted to examine the counts established at the output connections of the plurality of shift register means, said third detector means being operative in response to detecting a count representing the end of a bit period following a transition for which a transition output signal is produced by the first detector means to produce a corresponding output signal; and means coupled to the third detector means and to the input connections of the plurality of shift register means and operative in response to each output signal produced by the third detector means to reset the first stages of said plurality of shift register means.

Claim 18

A data sampling apparatus, comprising: sampling means having n-input connections for receiving n-binary coded signals comprising bits in corresponding bit periods, and further having an output connection, said sampling means being operative to repetitively sample the n-binary coded signals received at its input connections in succession, and to apply the sampled signals, each having a first bit value or a second bit value, to its output connection; a plurality of shift register means each having n-stages and each having an input connection and an output connection, the input connection of the first one of the plurality of shift register means being coupled to the output connection of the sampling means, and the output connection of each of the plurality of shift register means, with the exception of the last one of the plurality of shift register means being coupled to the input connection of the next shift register means; clock means coupled to the plurality of shift register means and operative to clock the plurality of shift register means whereby the sampled signals applied to the output connection of the sampling means are clocked into and along the plurality of shift register means, synchronous with the sampling of the binary coded signals by the sampling means, and whereby a set of the most recent sampled signals derived from each of the binary coded signals is caused to be stored in sets of parallel stages of the plurality of shift register means and to be clocked to the output connections of the pluralIty of shift register means, the number of sampled signals in each set being equal to the number of shift register means in the plurality of shift register means; first detector means coupled to the output connections of the plurality of shift register means and adapted to examine the sets of sampled signals clocked to the output connections of the plurality of shift register means, and first detector means being operative in response to detecting a particular set of sampled signals having particular values at the output connections of the plurality of shift register means indicating the occurrence of a transition in one of the binary coded signals from one of its bit values to the other of its bit values to produce a transition output signal; counting means coupled to the first detector means and having a plurality of output connections, said counting means being operative in response to a transition output signal produced by the first detector means to establish at its output connections successive combinations of output signals corresponding to the samples of the bit present in the bit period following the transition for which the transition output signal is produced by the first detector means, said combinations of output signals representing different counts, one of said counts representing a particular point in each bit period following a transition for which a transition output signal is produced by the first detector means; second detector means coupled to the output connections of the counting means and adapted to examine the counts established at the output connections of the counting means, said second detector means being operative in response to detecting a count representing the aforesaid particular point in a bit period following a transition for which a transition output signal is produced by the first detector means to produce a corresponding output signal; and output means coupled to the second detector means and to the output connection of a predetermined one of the plurality of shift register means, said output means being operative in response to an output signal produced by the second detector means corresponding to a count representing the aforesaid point in a bit period to receive the sampled signal at the output connection of the aforesaid shift register means, said sampled signal representing the value of the bit in said bit period.

Claim 19

A data sampling apparatus, comprising: sampling means having n-input connections for receiving n-binary coded signals comprising bits in corresponding bit periods, and further having an output connection, said sampling means being operative to repetitively sample the n-binary coded signals received at its input connections in succession, and to apply the sampled signals, each having a first bit value or a second bit value, to its output connection; a plurality of shift register means each having n-stages and each having an input connection and an output connection, the input connection of the first one of the plurality of shift register means being coupled to the output connection of the sampling means, and the output connection of each of the plurality of shift register means, with the exception of the last one of the plurality of shift register means being coupled to the input connection of the next shift register means; clock means coupled to the plurality of shift register means and operative to clock the plurality of shift register means whereby the sampled signals applied to the output connection of the sampling means are clocked into and along the plurality of shift register means, synchronous with the sampling of the binary coded signals by the sampling means, and whereby a set of the most recent sampled signals derived from each of the binary coded signals is caused to be stored in sets of parallel stages of the plurality of shift register means and to be clocked to the output connections of the pluralIty of shift register means, the number of sampled signals in each set being equal to the number of shift register means in the plurality of shift register means; first detector means coupled to the output connections of the plurality of shift register means and adapted to examine the sets of sampled signals clocked to the output connections of the plurality of shift register means, and first detector means being operative in response to detecting a particular set of sampled signals having particular values at the output connections of the plurality of shift register means indicating the occurrence of a transition in one of the binary coded signals from one of its bit values to the other of its bit values to produce a transition output signal; counting means coupled to the first detector means and having a plurality of output connections, said counting means being operative in response to a transition output signal produced by the first detector means to establish at its output connections successive combinations of output signals corresponding to the samples of the bit present in the bit period following the transition for which the transition output signal is produced by the first detector means, said combinations of output signals representing different counts, one of said counts representing a particular point in each bit period following a transition for which a transition output signal is produced by the first detector means; second detector means coupled to the output connections of the counting means and adapted to examine the counts established at the output connections of the counting means, said second detector means being operative in response to detecting a count representing the aforesaid particular point in a bit period following a transition for which a transition output signal is produced by the first detector means to produce a corresponding output signal; and output means coupled to the second detector means and to the output connection of a predetermined one of the plurality of shift register means, said output means being operative in response to an output signal produced by the second detector means corresponding to a count representing the aforesaid point in a bit period to receive the sampled signal at the output connection of the aforesaid shift register means, said sampled signal representing the value of the bit in said bit period.

Claim 20

A data sampling apparatus in accordance with claim 16 wherein: the counter means comprises: a. a second plurality of shift register means, each having n stages and each having an input connection and an output connection, the input connection of the first one of the second plurality of shift register means being coupled to the first detector means, and the output connection of each of the second plurality of shift register means, with the exception of the last one of the second plurality of shift register means, being coupled to the input connection of the next shift register means; and b. logic means coupled to the second plurality of shift register means and to the first detector means and operative when a transition output signal is produced by the first detector means to establish a counting mode of operation for the second plurality of shift register means whereby successive combinations of output signals are caused to be established at the output connections of the second plurality of of shift register means, said combinations representing different counts.

Claim 21

A data sampling apparatus in accordance with claim 17 wherein: the logic means includes an exclusive-or logic arrangement.

Claim 22

A data sampling apparatus in accordance with claim 18 wherein: the second detector means is coupled to the output connections of the second plurality of shift register means and is operative to produce an output signal in response to detecting a count established at the output connections representing the center of a bit period following a transition for which a Transition output signal is produced by the first detector means.

Claim 23

A data sampling apparatus in accordance with claim 19 wherein: another one of the counts established at the output connections of the second plurality of shift register means represents the end of each bit period following a transition for which a transition output signal is produced by the first detector means; and said data sampling apparatus further comprises: third detector means coupled to the output connections of the second plurality of shift register means and adapted to examine the counts established at the output connections of the second plurality of shift register means, said third detector means being operative in response to detecting a count representing said end of a bit period following a transition for which a transition output signal is produced by the first detector means to produce a corresponding output signal; and means coupled to the third detector means and to the input connections of the second plurality of shift register means and operative in response to each output signal produced by the third detector means to reset the first stages of said second plurality of shift register means.