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US3763382A Expired / Lapsed US ⏱️ 0.0 years remaining

Amplitude control circuit

Assignee: Sony Corp
•
Filing: 1972-03-01
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Granted: 1973-10-02
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Expires: 1992-03-01
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Abstract

Abstract A signal amplitude control circuit having a main signal transmission path and a shunt path comprising a variable impedance circuit having a plurality of series connected semiconductor elements whose impedances are varied by changing their biasing conditions in response to a control signal.

Inventors

  • 👤 T Horichi
  • 👤 Y Kanemoto

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-27 09:14
CPC Classifications
H; H03; H03G; H03G3/00; H03G3/20; H03G3/30; H03G3/3005; H03G3/301; H03G3/3015; H03G1/00; H03G1/0005; H03G1/0035

Claims Analysis

Total Claims: 12
Claim 1
Independent Claim 249 words
An amplitude control circuit comprising a signal transmission path having input and output terminals and a circuit ground, and means for providing a variable impedance shunt path between the input and output terminals of the transmission path and the circuit ground, the shunt path means including a first semiconductor device having first, second and third electrodes, a D.C. power source having first and second terminals, the second terminal being connected to the circuit ground, a first resistive element connected between the first electrode and the first terminal of the D.C. power source and a second resistive element connected between the second electrode and the circuit ground, the first and second resistive elements having substantially equal resistance values, at least a second and a third semiconductor device series connected between the first and the second electrodes of the first semiconductor device, each of the second and the third semiconductor devices having a junction of P-type and N-type semiconductor regions therein with the P-type region of one of the second and the third semiconductor devices being connected to the N-type region of the other of the second and the third semiconductor devices, means for connecting a point in the signal transmission path between the input and output terminals with a point between the series connected second and third semiconductor devices, and means for supplying a control signal to the third electrode to cause the first semiconductor device to be selectively saturated and unsaturated in response to variations of the control signal.
Claim 2
Dependent Claim 249 words
An amplitude control circuit comprising a signal transmission path having input and output terminals and a circuit ground, and means for providing a variable impedance shunt path between the input and output terminals of the transmission path and the circuit ground, the shunt path means including a first semiconductor device having first, second and third electrodes, a D.C. power source having first and second terminals, the second terminal being connected to the circuit ground, a first resistive element connected between the first electrode and the first terminal of the D.C. power source and a second resistive element connected between the second electrode and the circuit ground, the first and second resistive elements having substantially equal resistance values, at least a second and a third semiconductor device series connected between the first and the second electrodes of the first semiconductor device, each of the second and the third semiconductor devices having a junction of P-type and N-type semiconductor regions therein with the P-type region of one of the second and the third semiconductor devices being connected to the N-type region of the other of the second and the third semiconductor devices, means for connecting a point in the signal transmission path between the input and output terminals with a point between the series connected second and third semiconductor devices, and means for supplying a control signal to the third electrode to cause the first semiconductor device to be selectively saturated and unsaturated in response to variations of the control signal.
Claim 3
Dependent Claim 19 words
An amplitude control circuit as recited in claim 1, wherein the second and the third semiConductor devices comprise diodes.
Claim 4
Dependent Claim 46 words
An amplitude control circuit as recited in claim 1, wherein the second and the third semiconductor devices comprise a plurality of transistors, each transistor having at least one of its junctions connected in series with a junction of the opposite polarity of another of the transistors.
Claim 5
Dependent Claim 24 words
An amplitude control circuit as recited in claim 1, wherein the second and the third semiconductor devices comprise field effect transistors connected in series.
Claim 6
Dependent Claim 38 words
An amplitude control circuit as recited in claim 1, further comprising biasing means connected to the third electrode of the first semiconductor devive to maintain it in a saturated current condition in the absence of a control signal.
Claim 7
Dependent Claim 64 words
An amplitude control circuit as recited in claim 5, wherein the first semiconductor device is a transistor having base, emitter and collector electrodes, and the biasing means includes a third resistive element connected to the base of the transistor for biasing it to operate with a saturation current between its emitter and collector electrodes when no control signal is applied to the base electrode.
Claim 8
Dependent Claim 46 words
An amplitude control circuit as recited in claim 6, wherein the second and the third semiconductor devices comprise diodes connected in series with the same polarity direction and the emitter of the transistor is connected through the series connected diodes to the collector of the transistor.
Claim 9
Dependent Claim 179 words
An amplitude control circuit comprising: a. a signal transmission path having input and output terminals, b. a source of direct current, c. first and second resistors, d. a first transistor having base, emitter and collector electrodes, each being connected with a separate end of the D.C. power source through one of the first and the second resistors, e. a control signal input terminal connected to the base of the first transistor, f. a second transistor connected with the emitter of the first transistor and a third transistor connected with the collector of the first transistor, means for biasing each of the second and the third transistors to operate in the emitter follower configuration, g. a plurality of series-connected semiconductor elements connected with the same polarity direction between the emitters of the second and the third transistors, each of the elements having a junction of P-type and N-type semiconductor regions therein, and h. a connecting point between the series connected semiconductor elements and means for connecting the point with the signal transmission path between the input and the output terminals.
Claim 10
Dependent Claim 179 words
An amplitude control circuit comprising: a. a signal transmission path having input and output terminals, b. a source of direct current, c. first and second resistors, d. a first transistor having base, emitter and collector electrodes, each being connected with a separate end of the D.C. power source through one of the first and the second resistors, e. a control signal input terminal connected to the base of the first transistor, f. a second transistor connected with the emitter of the first transistor and a third transistor connected with the collector of the first transistor, means for biasing each of the second and the third transistors to operate in the emitter follower configuration, g. a plurality of series-connected semiconductor elements connected with the same polarity direction between the emitters of the second and the third transistors, each of the elements having a junction of P-type and N-type semiconductor regions therein, and h. a connecting point between the series connected semiconductor elements and means for connecting the point with the signal transmission path between the input and the output terminals.
Claim 11
Dependent Claim 36 words
An amplitude control circuit as recited in claim 8, further comprising means responsive to the signal at the output terminal of the signal transmission path for feeding a control signal to the control signal input terminal.
Claim 12
Dependent Claim 64 words
An amplitude control circuit as recited in claim 9, further comprising means for biasing the first transistor to maintain it in a saturated current condition in the absence of a control signal and wherein the feeding means includes a rectifying circuit for producing a control signal in response to the output signal and for applying the control signal to the control signal input terminal.

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1976-10-01 1977-04-02 1977-10-02 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1980-10-01 1981-04-02 1981-10-02 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1984-10-01 1985-04-02 1985-10-02 $7700.00 Window Closed / Lapsed

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