Abstract A pair of transistors are connected in parallel with the emitters of the transistors connected to ground and the collectors connected together and to a common junction which in turn is connected through a resistor to an output terminal. A first input terminal is connected through an amplifier and a resistor to the common junction. The output of the amplifier is also connected through a diode to the base of the first transistor. The base is also connected through a resistor to a negative biasing voltage. The base of the second transistor is connected through a resistor to a negative biasing voltage. The base of the transistor is also connected through a diode to a second input terminal. The transistors are biased such that a signal appearing on the first input terminal is determinative of the amount of signal compensation appearing at the output terminal and a signal appearing at the second input terminal is determinative of the existence of the compensation.
A compensator circuit comprising: a. a first input terminal for receiving varying first input signals; b. a first transistor and a second transistor, the emitters of said transistors being connected to each other and the collectors of said transistors being connected to each other, said collectors being also connected to an output terminal, said first input terminal being connected to the base of said first transistor; c. a resistor connected between said first terminal and said output terminal; and d. a second input terminal for receiving varying second input signals, wherein said first varying signals are different from said second varying signals, connected to the base of said second transistor, said transistors being biased such that a signal appearing at said first input terminal is determinative of the amount of signal compensation appearing at the output terminal and a signal appearing at said second input terminal is determinative of the existence of said compensation.
Claim 2
Dependent Claim
154 words
A compensator circuit comprising: a. a first input terminal for receiving varying first input signals; b. a first transistor and a second transistor, the emitters of said transistors being connected to each other and the collectors of said transistors being connected to each other, said collectors being also connected to an output terminal, said first input terminal being connected to the base of said first transistor; c. a resistor connected between said first terminal and said output terminal; and d. a second input terminal for receiving varying second input signals, wherein said first varying signals are different from said second varying signals, connected to the base of said second transistor, said transistors being biased such that a signal appearing at said first input terminal is determinative of the amount of signal compensation appearing at the output terminal and a signal appearing at said second input terminal is determinative of the existence of said compensation.