US3761824A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Pulse frequency divider
Assignee: Siemens AG
•
Filing: 1971-11-23
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Granted: 1973-09-25
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Expires: 1991-11-23
Abstract
Abstract A frequency divider has an AND gate having an output connected in common to the reset inputs of a chain circuit of bistable flip flops. The frequency divider drives a presettable number of pulses of an input pulse train from the flip flops via a selector switch connected to their outputs. The outputs of the flip flops are connected to the inputs of the AND gate via preselectable circuit connections for setting the denominator of the number of pulses.
Inventors
- 👤 R Stark
- 👤 G Steinmuller
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 04:16
CPC Classifications
H; H03; H03K; H03K23/00; H03K23/64; H03K23/66; G; G06; G06F; G06F7/00; G06F7/60; G06F7/68
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
184 words
A pulse frequency divider for deriving a variable number of pulses of an input pulse train from a chain circuit of bistable flip flops via selector switch means connected to the outputs of the flip flops, each of said flip flops having an input, a reset input, an output and an inverse output, the number of pulses having a numerator and a denominator, said frequency divider comprising an AND gate having inputs and having output connected to the reset inputs of the flip flops; preselectable circuit connecting means; means connecting the outputs of the flip flops to the inputs of the AND gate via the preselectable circuit connecting means for setting the denominator; additional preselectable circuit connecting means; differentiating members; an OR gate having inputs connected to the negative terminal of the voltage source and an output for providing the numerator frequency; a voltage source having a positive terminal and a negative terminal; and means connecting the outputs of the flip flops to the inputs of the OR gate via the differentiating members and the additional preselectable circuit connecting means for setting the numerator.
Claim 2
Dependent Claim
184 words
A pulse frequency divider for deriving a variable number of pulses of an input pulse train from a chain circuit of bistable flip flops via selector switch means connected to the outputs of the flip flops, each of said flip flops having an input, a reset input, an output and an inverse output, the number of pulses having a numerator and a denominator, said frequency divider comprising an AND gate having inputs and having output connected to the reset inputs of the flip flops; preselectable circuit connecting means; means connecting the outputs of the flip flops to the inputs of the AND gate via the preselectable circuit connecting means for setting the denominator; additional preselectable circuit connecting means; differentiating members; an OR gate having inputs connected to the negative terminal of the voltage source and an output for providing the numerator frequency; a voltage source having a positive terminal and a negative terminal; and means connecting the outputs of the flip flops to the inputs of the OR gate via the differentiating members and the additional preselectable circuit connecting means for setting the numerator.
Claim 3
Dependent Claim
25 words
A pulse frequency divider as claimed in claim 1, wherein the AND gate has an additional input connected to the surfaces preselectable circuit connecting means.
Claim 4
Dependent Claim
80 words
A pulse frequency divider as claimed in claim 1, wherein the selection switch means comprises plug-in circuit connecting means, and further comprising NAND gates having inputs connected to the outputs and inverse outputs of the flip flops and having outputs, and additional NAND gate having inputs and an output for providing the numerator frequency, and means connecting the outputs of the NAND gates to the inputs of the additional NAND gate via the plug-in circuit means for setting the numerator.
Claim 5
Dependent Claim
41 words
A pulse frequency divider as claimed in claim 3, wherein each of the NAND gates has an additional input, and further comprising input means connected to the additional input of each of the NAND gates for supplying an input pulse train.
Claim 6
Dependent Claim
153 words
A pulse frequency divider as claimed in claim 3, differentiating members, an OR gate having inputs and an output for providing the numerator frequency, means connecting the outputs oF the flip flops to the inputs of the OR gate via the differentiating members and the plug-in circuit connecting means for setting the numerator, further comprising a voltage source having a positive terminal and a negative terminal, a first plurality of resistors, a second plurality of resistors, the differentiating members including a third plurality of resistors, means connecting the inputs of the AND gate to the positive terminal of the voltage source via the first plurality of resistors, means connecting the inputs of the OR gate to the negative terminal of the voltage source via the second plurality of resistors and means connecting the inputs of the additional NAND gate to the positive terminal of the voltage source via the third plurality of resistors.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-09-24 | 1977-03-26 | 1977-09-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-09-24 | 1981-03-26 | 1981-09-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-09-24 | 1985-03-26 | 1985-09-25 | $7700.00 | Window Closed / Lapsed |