US3660767A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Frequency divider circuit system
Assignee: Panasonic Holdings Corp
•
Filing: 1969-12-18
•
Granted: 1972-05-02
•
Expires: 1989-12-18
Abstract
Abstract A frequency divider wherein the pulse input having been delayed by a predetermined time interval is impressed upon a plurality of cascade connected flip-flops, and the output from each of the flip-flops is fed to an AND gate to which is also fed the input which has not passed through the delay circuit to produce a resultant AND output to be fed back to each of the required flipflops, thereby increasing the upper limit of the frequency to be divided and practically eliminating the danger of a malfunction in the system.
Inventors
- 👤 Hirokazu Yoshino
- 👤 Tomio Yoshida
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 15:51
CPC Classifications
H; H03; H03B; H03B19/00
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
108 words
A frequency divider, comprising: means, including a delay circuit, for delaying an input pulse signal applied to said frequency divider; a counter circuit including a plurality of cascade connected flip-flops; means applying the delayed input pulse signal to at least a portion of said plurality of flip-flops; means, including an AND circuit for producing an AND product of the non-delayed input pulse signal and the outputs of said plurality of flip-flops; and means, including a plurality of gate circuits, each connected to a corresponding one of said plurality of flip-flops, for selectively applying the output of said AND circuit to said corresponding one of said plurality of flip-flops.
Claim 2
Dependent Claim
108 words
A frequency divider, comprising: means, including a delay circuit, for delaying an input pulse signal applied to said frequency divider; a counter circuit including a plurality of cascade connected flip-flops; means applying the delayed input pulse signal to at least a portion of said plurality of flip-flops; means, including an AND circuit for producing an AND product of the non-delayed input pulse signal and the outputs of said plurality of flip-flops; and means, including a plurality of gate circuits, each connected to a corresponding one of said plurality of flip-flops, for selectively applying the output of said AND circuit to said corresponding one of said plurality of flip-flops.
Claim 3
Dependent Claim
58 words
A frequency divider according to claim 1, further comprising a second AND circuit, having said delayed input pulse signal as a first input and the output of a first of said cascade connected flip-flops as a second input, the output of said second AND circuit being connected to the input of a second of said cascade connected flip-flops.
Claim 4
Dependent Claim
93 words
A frequency divider, comprising: means, including a delay circuit, for delaying an input pulse signal; a first counter circuit including a plurality of cascade connected flip-flops; means applying the delayed input pulse signal to at least a portion of said plurality of flip-flops; a second counter circuit including at least one flip-flop; means, including an AND circuit, for producing an AND product of the non-delayed input pulse signal and the output of said first counter circuit; and means applying the output of said AND circuit to the input of said second counter circuit.
Claim 5
Dependent Claim
93 words
A frequency divider, comprising: means, including a delay circuit, for delaying an input pulse signal; a first counter circuit including a plurality of cascade connected flip-flops; means applying the delayed input pulse signal to at least a portion of said plurality of flip-flops; a second counter circuit including at least one flip-flop; means, including an AND circuit, for producing an AND product of the non-delayed input pulse signal and the output of said first counter circuit; and means applying the output of said AND circuit to the input of said second counter circuit.
References Cited (Backward Citations)
US2924816A
Cited
US3041476A
Cited
US3076601A
Cited
US3064890A
Cited
US3212010A
Cited
US3268740A
Cited
US3300724A
Cited
US3369183A
Cited
US3408595A
Cited
US3518553A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-05-02 | 1975-11-01 | 1976-05-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-05-02 | 1979-11-01 | 1980-05-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-05-02 | 1983-11-01 | 1984-05-02 | $7700.00 | Window Closed / Lapsed |