Timing pulse generator

Claim 2

A timIng pulse generator comprising: a plurality of two-phase shift registers; first means, connected to at least one of said shift registers, for supplying thereto a read-in pulse and a memory pulse; second means, responsive to said first means and to the outputs of selected stages of said shift register for recirculating the output of a first predetermined stage of said one shift register; and third means, responsive to the output of a second predetermined stage of said one shift register and to a read-in pulse generated by said first means for providing a read-in pulse for another of said plurality of shift registers other than said one shift register.

Claim 3

A timing pulse generator according to claim 1, wherein said first predetermined stage and said second predetermined stage of said one shift register are the same.

Claim 4

A timing pulse generator according to claim 1, wherein said second means comprises a first logic circuit responsive to the outputs of said selected stages and connected to the input of a third predetermined stage of said one shift register for supplying an input to said third predetermined stage only when the outputs of each of said selected stages are the same.

Claim 5

A timing pulse generator according to claim 3, wherein said second means comprises an NOR circuit.

Claim 6

A timing pulse generator according to claim 3, wherein said third means comprises an AND circuit.

Claim 7

A timing pulse generator according to claim 1, wherein said selected stages of said shift register are exclusive of said first and second predetermined stages.

Claim 8

A timing pulse generator according to claim 3, wherein said selected stages of said shift register are exclusive of said first and second predetermined stages and inclusive of said third predetermined stage.

Claim 9

A timing pulse generator according to claim 1, further including a connection between said first means and each of said shift registers within said plurality of shift registers for supplying memory pulses from said first means to each of said shift registers.

Claim 10

A timing pulse generator according to claim 1, wherein each stage of each of shift registers comprises: a first field effect transistor, the source electrode of which is connected to the input terminal of said stage and the gate electrode of which is connected to a read-in pulse terminal for receiving read-in pulses; a first pair of series-connected field effect transistors connected between a pair of bias terminals, the gate electrode of one of said transistors of said first pair being connected to the drain electrode of said first field effect transistor; a second pair of series-connected field effect transistors connected between said pair of bias terminals, the common electrode junction of said second pair being the output terminal of said shift register stage; and a second field effect transistor connected in series between the common electrode junction of said first pair of series connected field effect transistors and the gate electrode of one of the transistors of said second pair of series-connected field effect transistors and having its gate electrode connected to a memory pulse input terminal for receiving said memory pulses in said stage.

Claim 11

A timing pulse generator comprising a plurality of two-phase shift registers, pulse generating means for generating alternately read-in pulses for the first shift register and memory pulses for all shift registers, NOR circuits arranged correspondingly to each of said shift registers and supplied with the output from all stages excluding the last stage of a respective shift registers so as to furnish the output thereof to the first stage of the corresponding shift register, and AND circuits arranged correspondingly to each of said shift registers for furnishing the logical product of the output of the last stage of each shift register and the read-in pulse to the subsequent shift register as a read-in pulse.

Claim 12

A timing pulse generator comprising a plurality of two-phase shift registers, pulse generating means for generating alternately read-in pulses for the first shift register and memory pulses for all shift registers, NOR circuits arranged correspondingly to each of said shift registers and supplied with the output from all stages excluding the last stage of a respective shift registers so as to furnish the output thereof to the first stage of the corresponding shift register, and AND circuits arranged correspondingly to each of said shift registers for furnishing the logical product of the output of the last stage of each shift register and the read-in pulse to the subsequent shift register as a read-in pulse.