Patent US4873771A successfully refreshed from Google Patents.
Patent US3754235A successfully refreshed from Google Patents.
US3754235A
Expired / Lapsed
US
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Digital to analog converter
Assignee: Allen Bradley Co LLC
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Filing: 1971-03-01
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Granted: 1973-08-21
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Expires: 1991-03-01
Abstract
Abstract There is provided a digital to analog converter whose transfer function can be made either linear or non-linear depending upon whether or not the clock pulses provided therefore have a constant or a variable frequency. This provides a means for implementing a quadratic gain characteristic so that when used with a positioning servo the performance thereof is greatly enhanced.
Inventors
- 👤 E Dummermuth
- 👤 R Walters
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 21:18
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/12; H03M1/1205
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
221 words
A system for converting a digital number into an analog value comprising: means for establishing a transfer signal followed by a sampling signal having a duration representative of a desired sampling interval, counter means, means responsive to said transfer signal for forcing said counter means to assume a count state representative of said digital number, a source of clock signals, means responsive to said sampling signal to enable said clock signals to be applied to said counter means to cause it to count from the assumed count state to a predetermined count state, means for detecting when said counter means has reached said predetermined count state and producing an end of count signal representative thereof, flip-flop means responsive to said clock signals being applied to said counter to initiate a pulse and responsive to said end of count signal or to the end of said sampling signal to terminate said pulse whereby the width of the pulse output of said flip-flop means is an analog representation of said digital number when said pulse is terminated by said end of count signal, and whereby the width of said pulse output represents the width of said sampling signal when said pulse is terminated responsive to the end of said sampling signal indicative that said digital number exceeds the active range of said system.
Claim 2
Independent Claim
221 words
A system for converting a digital number into an analog value comprising: means for establishing a transfer signal followed by a sampling signal having a duration representative of a desired sampling interval, counter means, means responsive to said transfer signal for forcing said counter means to assume a count state representative of said digital number, a source of clock signals, means responsive to said sampling signal to enable said clock signals to be applied to said counter means to cause it to count from the assumed count state to a predetermined count state, means for detecting when said counter means has reached said predetermined count state and producing an end of count signal representative thereof, flip-flop means responsive to said clock signals being applied to said counter to initiate a pulse and responsive to said end of count signal or to the end of said sampling signal to terminate said pulse whereby the width of the pulse output of said flip-flop means is an analog representation of said digital number when said pulse is terminated by said end of count signal, and whereby the width of said pulse output represents the width of said sampling signal when said pulse is terminated responsive to the end of said sampling signal indicative that said digital number exceeds the active range of said system.
Claim 3
Dependent Claim
34 words
A system as recited in claim 1 wherein said source of clock signals includes means for changing the frequency of said clock signals in a predetermined pattern over the duration of said sampling interval.
Claim 4
Dependent Claim
26 words
A systeM as recited in claim 2 wherein said predetermined frequency pattern of clock signals provides a quadratic gain characteristic for said digital to analog converter.
Claim 5
Dependent Claim
91 words
A system as recited in claim 1 wherein said digital number has a digit position thereof assigned to represent whether said digital number is positive or negative, means responsive to a digital number being positive for providing a first output signal and to a digital number being negative for providing a second output signal, gate means responsive to said first output signal for causing said counter to count in a descending count mode and responsive to said second output signal for causing said counter to count in an ascending count mode.
Claim 6
Dependent Claim
101 words
A system as recited in claim 2 wherein said means for changing the frequency of said clock signals over the duration of said sampling interval incudes means responsive to said sample signal for dividing each sampling interval into a plurality of successive intervals and providing an interval count signal over each interval, means to which said clock signals are applied for generating a plurality of different frequency clock signals, and gate means to which said interval count signals and plurality of different frequency clock signals are applied for selecting in succession different ones of said plurality of different frequency clock signals.
Claim 7
Independent Claim
297 words
A system for determining the transfer characteristic of a digital to analog converter which converts digital numbers to analog values comprising: means for establishing a transfer signal followed by a sampling signal having a duration representative of a desired sampling interval, counter means, a source of digital numbers, means responsive to said transfer signal for forcing said counter means to assume a count state representative of a digital number from said source, means responsive to said sampling signal for establishing successive intervals over the duration of said sampling interval and providing an interval count signal over each interval, means for generating a plurality of different predetermined frequency clock signals, gate means to which said interval count signals and said plurality of different predetermined frequency clock signals are applied for successively selecting and outputting different ones of said plurality of different predetermined frequency clock signals in accordance with the transfer characteristic desired for said digital to analog converter, means responsive to said transfer signal for applying the output of said gate means to said counter means to cause it to count from its assumed count state to a predetermind count state, means for detecting when said counter means has reached said predetermined count state and producing an end of count signal at that time, flip-flop means responsive to said clock signals being applied to said counter to initiate a pulse and responsive to the said sampling signal being terminated or to said end of count signal to terminate said pulse whereby the width of the pulse output of the flip-flop means is an analog representation of said digital number when said flip-flop means terminates said pulse responsive to said end of count signal and in either case is not linearly related to the size of said digital number.
Claim 8
Independent Claim
297 words
A system for determining the transfer characteristic of a digital to analog converter which converts digital numbers to analog values comprising: means for establishing a transfer signal followed by a sampling signal having a duration representative of a desired sampling interval, counter means, a source of digital numbers, means responsive to said transfer signal for forcing said counter means to assume a count state representative of a digital number from said source, means responsive to said sampling signal for establishing successive intervals over the duration of said sampling interval and providing an interval count signal over each interval, means for generating a plurality of different predetermined frequency clock signals, gate means to which said interval count signals and said plurality of different predetermined frequency clock signals are applied for successively selecting and outputting different ones of said plurality of different predetermined frequency clock signals in accordance with the transfer characteristic desired for said digital to analog converter, means responsive to said transfer signal for applying the output of said gate means to said counter means to cause it to count from its assumed count state to a predetermind count state, means for detecting when said counter means has reached said predetermined count state and producing an end of count signal at that time, flip-flop means responsive to said clock signals being applied to said counter to initiate a pulse and responsive to the said sampling signal being terminated or to said end of count signal to terminate said pulse whereby the width of the pulse output of the flip-flop means is an analog representation of said digital number when said flip-flop means terminates said pulse responsive to said end of count signal and in either case is not linearly related to the size of said digital number.
Claim 9
Dependent Claim
26 words
A system as recited in claim 6 wherein said predetermined frequency pattern of clock signals provides a quadratic gain characteristic for said digital to analog converter.
Claim 10
Dependent Claim
91 words
A system as recited in claim 6 wherein said digital number has a digit position thereof assigned to represent whether said digital number is positive or negative, means responsive to a digital number being positive for providing a first output signal and to a digital number being negative for providing a second output signal, gate means responsive to said first output signal for causing said counter to count in a descending count mode and responsive to said second output signal for causIng said counter to count in an ascending count mode.
Claim 11
Dependent Claim
69 words
A system as recited in claim 6 including means for determining whether said digital number is positive and producing a first signal representative thereof, or negative and producing a second signal representative thereof, and means to which the pulse output of said flip-flop means is applied for inverting the polarity of said pulse output responsive to said second signal and leaving the polarity uninverted responsive to said first signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-08-20 | 1977-02-19 | 1977-08-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-08-20 | 1981-02-19 | 1981-08-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-08-20 | 1985-02-19 | 1985-08-21 | $7700.00 | Window Closed / Lapsed |