US3573803A
Expired / Lapsed
US
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Time division multiplex digital-to-analog converter
Assignee: International Standard Electric Corp
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Filing: 1969-01-24
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Granted: 1971-04-06
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Expires: 1989-01-24
Abstract
Abstract A plurality of binary counters are provided, each of which are assigned to a different channel code, and arranged in two groups. A master binary counter advancing in synchronism with the timing of the input codes and logic circuitry associated with each counter cooperate to cause the counters of one group to convert the code signals of that group and simultaneously connect the counters of the other group in series and to function as shift registers to store serial input codes. The functions of the group of counters are then reversed. The counters of a group in which codes have been previously stored cooperate with the master binary counter and a bistable device coupled to each counter to produce PWM pulses which are filtered to reproduce the analog signals represented by the stored codes.
Inventors
- 👤 Andre Edouard Joseph Chatelon
- 👤 Didier Charles Strube
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 18:43
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/12; H03M1/22
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
456 words
A digital-to-analog converter comprising: INPUT MEANS for m digital codes in serial form, each of said codes having n digits, where both m and n are integers greater than one; master binary counting means having a plurality of output signals coupled to said input means operating in synchronism with the timing of the digits of said codes; a first group of m/2 binary counting means coupled to said input means and said master counting means responsive to selected ones of said output signals to connect each of said counting means of said first group as independent counting means for a first given time interval and to connect each of said counting means of said first group as a shift register and in series with each other for a second given time interval different than said first time interval, said counting means of said first group being loaded with m/2 of said codes during said second time interval; a second group of m/2 binary counting means coupled to said input means and said master counting means coupled to said input means and said master counting means responsive to said selected ones of said output signals to connect each of said counting means of said second group as independent counting means for said second time interval and to connect each of said counting means of said second group as a shift register and in series with each other for said first time interval, said counting means of said second group being loaded with the remaining m/2 of said codes during said first time interval; first m/2 logic circuit means, each of said first logic circuit means being coupled to a different one of said counting means of said first group and in common to said master counting means responding to said selected ones of said output signals, others of said output signals and the code stored in the associated one of said counting means of said first group during said first time interval to produce a pulse width modulated signal having a width representative of the code stored in said associated one of said counting means of said first group; and second m/2 logic circuit means, each of said second logic circuit means being coupled to a different one of said counting means of said second group and in common to said master counting means responding to said selected ones of said output signals, others of said output signals and the code stored in the associated one of said output counting means of said second group during said second time interval to produce a pulse width modulated signal having a Width representative of the code stored in said associated one of said counting means of said second group.
Claim 2
Dependent Claim
456 words
A digital-to-analog converter comprising: INPUT MEANS for m digital codes in serial form, each of said codes having n digits, where both m and n are integers greater than one; master binary counting means having a plurality of output signals coupled to said input means operating in synchronism with the timing of the digits of said codes; a first group of m/2 binary counting means coupled to said input means and said master counting means responsive to selected ones of said output signals to connect each of said counting means of said first group as independent counting means for a first given time interval and to connect each of said counting means of said first group as a shift register and in series with each other for a second given time interval different than said first time interval, said counting means of said first group being loaded with m/2 of said codes during said second time interval; a second group of m/2 binary counting means coupled to said input means and said master counting means coupled to said input means and said master counting means responsive to said selected ones of said output signals to connect each of said counting means of said second group as independent counting means for said second time interval and to connect each of said counting means of said second group as a shift register and in series with each other for said first time interval, said counting means of said second group being loaded with the remaining m/2 of said codes during said first time interval; first m/2 logic circuit means, each of said first logic circuit means being coupled to a different one of said counting means of said first group and in common to said master counting means responding to said selected ones of said output signals, others of said output signals and the code stored in the associated one of said counting means of said first group during said first time interval to produce a pulse width modulated signal having a width representative of the code stored in said associated one of said counting means of said first group; and second m/2 logic circuit means, each of said second logic circuit means being coupled to a different one of said counting means of said second group and in common to said master counting means responding to said selected ones of said output signals, others of said output signals and the code stored in the associated one of said output counting means of said second group during said second time interval to produce a pulse width modulated signal having a Width representative of the code stored in said associated one of said counting means of said second group.
Claim 3
Dependent Claim
87 words
A converter according to claim 1, wherein said master counting means includes: a binary counter having (n+1) stages coupled in series with each other and said input means, the (n+1) th stage of said series coupled stages providing said selected ones of said output signals and the first n stages of said series coupled stages providing certain ones of said others of said output signals; and a decoder coupled to predetermined ones of said (n+1) stages to produce the remainder of said others of said output signals.
Claim 4
Dependent Claim
111 words
A converter according to claim 1, wherein each of said counting means of said first and second groups include: a binary counter having n stages coupled in series with each other; and a coincidence type logic circuit coupled to said master counting means and the input of said binary counter responsive to the appropriate one of said selected ones of said output signals during the appropriate one of said first and second time intervals to connect said binary counters of each of said first and second groups in series with each other and said input means and to load each of said binary counters with an associated one of said codes.
Claim 5
Dependent Claim
21 words
A converter according to claim 3, wherein each of said stages of each of said binary counters include a JK flip-flop.
Claim 6
Dependent Claim
276 words
A converter according to claim 3, wherein said input means includes first means to provide said codes, and second means to provide the complement of said codes; each of said stages of each of said binary counters include a first input and a first output for said codes, and a second input and a second output for said complement of said codes; said first output being coupled to said first input and said second output being coupled to said second input of adjacent ones of said stages; and said coincidence-type logic circuit includes; a first AND gate coupled between said first means and said first input of the first stage of the first binary counter of each of said first and second groups responsive to said one of said selected ones of said output signals; a second AND gate coupled between said second means and said second input of the first stage of the first binary counter of each of said first and second groups responsive to said one of said selected ones of said output signals; a third AND gate coupled between said first output of the last stage and said first input of the first stage of each adjacent ones of said binary counters of each of said first and second groups responsive to said one of said selected ones of said output signals; and a fourth AND gate coupled between said second output of the last stage and said second input of the first stage of each adjacent ones of said binary counters of each of said first and second groups responsive to said one of said selected ones of said output signals.
Claim 7
Dependent Claim
219 words
A converter according to claim 3, wherein each of said first and second logic circuit means includes: n AND gates each being coupled to said master counting means and a different one of said n stages of an associated one of said binary counters, each of said AND gates being responsive to the appropriate one of said selected ones of said output signals during the appropriate one of said first and second time intervals, a different one of certain ones of said others of said output signals and selected digits of the code stored in said associated one of said binary counters; a first additional AND gate coupled to said master counting means and the last of said n stages of said associated one of said binary counters responsive to an output signal of said last of said n stages, said appropriate one of said selected ones of said output signals and selected digits of the code stored in said associated one of said biNary counters; a second additional AND gate coupled to said master counting means responsive to said appropriate one of said selected ones of said output signals and another one of said others of said output signals, and a flip-flop coupled to said first and second additional AND gates to produce said pulse width modulated signal.
Claim 8
Dependent Claim
180 words
A converter according to claim 1, wherein each of said first and second logic circuit means includes: n coincidence devices coupled to each of said counting means of each of said first and second groups, each of said devices being responsive to one of said selected ones of said output signals, a different one of certain ones of said others of said output signals and selected digits of the code stored in said associated one of said counting means; a first additional coincidence device coupled to the output of each of said counting means of each of said first and second groups responsive to an output of said counting means and at least selected digits of the code stored in said associated one of said counting means; a second additional coincidence device coupled to said master counting means responsive to the other of said selected ones of said output signals and another one of said others of said output signals; and a bistable device coupled to said first and second additional coincidence devices to produce said pulse width modulated signal.
Claim 9
Dependent Claim
16 words
A converter according to claim 7, wherein each of said coincidence devices include an AND gate.
Claim 10
Dependent Claim
17 words
A converter according to claim 7, wherein each of said n coincidence devices include an INHIBIT gate.
Claim 11
Dependent Claim
416 words
A converter according to claim 1, wherein said master counting means includes: a first binary counter having (n+1) stages coupled in series with each other and said input, the (n+1) th stage of said series coupled stages providing said selected ones of said output signals and the first n stages of said series coupled stages providing certain ones of said others of said output signals; and a decoder coupled to predetermined ones of said (n+1) stages to produce the remainder of said others of said output signals; each of said counting means of said first and second groups include a second binary counter having n stages coupled in series with each other, and a coincidence-type logic circuit coupled to said first binary counter and the input of said second binary counter responsive to the appropriate one of said selected of said output signals during the appropriate one of said first and second time intervals to connect said second binary counters of each of said first and second groups in series with each other and said input means and to load each of said second binary counters with an associated one of said codes; and each of said first and second logic circuit means includes n AND gates each being coupled to said first binary counter and a different one of said n stages of an associated one of said second binary counters, each of said AND gates being responsive to the appropriate one of said selected ones of said output signals during the appropriate one of said first and second time intervals, a different one of said certain ones of said others of said output signals and selected digits of the code stored in said associated one of said secondary binary counters; a first additional AND gate coupled to said first binary counter and the last of said n stages of said associated one of said second binary counters responsive to an output signal of said last of said n stages, said appropriate one of said selected ones of said output signals and selected digits of the code stored in said associated one of said second binary counters; a second additional AND gate coupled to said first binary counter and said decoder responsive to said appropriate one of said selected ones of said output signals and one of sAid remainder of said other of said output signals; and a flip-flop coupled to said first and second additional AND gates to produce said pulse width modulated signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-04-05 | 1974-10-05 | 1975-04-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-04-05 | 1978-10-05 | 1979-04-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-04-05 | 1982-10-05 | 1983-04-06 | $7700.00 | Window Closed / Lapsed |