Poly-silicon electrodes for c-igfets

Claim 1

The method recited in claim 1 and further including leaving a portion of the gate oxide layer under portions of each polycrystalline electrode to delimit the area of diffusion of said source and drain regions through said polycrystalline electrodes.

Claim 3

A method for making insulated gate field-effect transistors so as to minimize the area at the active device necessary for contacting the source and drain regions thereof and so as to enable the probing and testing of intermediate structures made during fabrication of said insulated gate field-effect transistors comprising the steps of: providing a semiconductor substrate of a first conductivity type with a first insulating layer opened so as to expose a region where the active components of an insulated gate field-effect transistor are to be formed; forming a first oxide layer on said exposed region, said first oxide layer being patterned so as to expose areas on said substrate corresponding in position to the positions of the source and drain regions to be made; forming a layer of polycrystalline silicon over the structure thus formed; patterning said polycrystalline silicon layer so as to form source, drain and gate electrodes, portions of said source and drain electrodes overlying portions of the locations at which source and drain regions are to be formed; diffusing into said source and drain regions and also into said polycrystalline silicon layer a dopant having a conductivity type opposite that of said substrate, portions of said source and drain regions being diffused through portions of overlying polycrystalline silicon electrodes, whereby said patterned polycrystalline silicon layer is doped highly enough such that portions thereof serve as electrodes, whereby said source and drain regions are formed in ohmic contact with respective electrodes, portions of said source and drain regions having been doped through portions of corresponding electrodes, and whereby said structure may be probed after said diffusion step for insulated gate field-effect transistor properties.

Claim 6

A method for making insulated gate field-effect transistors so as to minimize the area at the active device necessary to contacting the source and drain regions thereof and so as to enable the probing and testing of intermediate structures made during fabrication of said insulated gate field-effect transistors comprising the steps of: providing a semiconductor substrate of a first conductivity type with a first insulating layer opened so as to expose a region where the active components of an insulated gate field-effect transistor are to be formed; forming a first oxide layer on said exposed region, said first oxide layer being patterned so as to expose areas on said substrate corresponding in position to the positions of the source and drain regions to be made, said first oxide layer being patterned to form an oversized gate oxide region; forming a layer of polycrystalline silicon over the structure thus formed; patterning said polycrystalline silicon layer so as to form source, drain and gate electrodes, said gate electrode being smaller than said oversized gate oxide region; forming a second oxide layer over the structure thus formed; forming a mask over said second oxide layer; opening said mask over all of said patterned polycrystalline silicon and over those areas at which active elements of said insulated gate field-effect transistor are to be formed; etching said second oxide layer through the openings in said mask with an etchant that does not attack polycrystalline silicon, whereby said patterned polycrystalline silicon is exposed and said substrate is exposed in regions where said source and drain are to be made, the gate polycrystalline silicon serving as an etch mask such that both the gate oxide and adjacent edges of the source and drain regions to be formed are aligned with said gate polycrystalline silicon electrode; and diffusing atoms of a type opposite that of said substrate into said polycrystalline silicon electrodes and into the exposed portions of said substrate, whereby said patterned polycrystalline silicon layer is doped highly enough such that portions thereof serve as electrodes, whereby said source and drain regions are formed in ohmic contact with respective electrodes, portions of said source and drain regions having been doped through portions of corresponding electrodes, and whereby said structure may be probed after said diffusion step for insulated gate field effect transistor properties.